Sequence Control Circuit for Abnormal Power-Down Protection
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Solution Overview
Problem
In server systems, abnormal power-downs due to sudden PSU failures lead to uncontrollable power-downs and voltage overshoots, risking component damage due to the mismatched power-down speeds of power and enable ends in DC power chips.
Innovation Solution
A sequence control circuit comprising a signal indication circuit, a control/isolation circuit with two-stage MOS transistors, and an energy storage circuit, which rapidly switches the enable signal to a low state and provides reserve power to prevent voltage overshoot by performing a logic AND operation on multiple power-down monitoring signals and using capacitive energy storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the power-down speed of the power end VCC is increased to respond quickly to abnormal power-down, then the response speed is improved, but the output voltage overshoots abnormally causing component damage
Solution Approach 1:
The patent applies preliminary action by detecting power-down conditions in advance through monitoring circuits and proactively controlling the enable end to switch off before the power end voltage drops completely. This提前 control prevents the voltage overshoot from occurring in the first place, resolving the contradiction between fast response and preventing harmful overshoot.
Solution Approach 2:
The enable end of the DC power chip serves as an intermediary control element between the power end and the load. By controlling the enable end to switch off first, it mediates the power-down process to prevent direct voltage overshoot on the power end, thus resolving the contradiction between fast power-down response and preventing component damage.
2Loss of time
If the voltage drops directly in case of abnormal power-down, then the response time is reduced, but the main board cannot execute shutdown sequence normally and all DC power supplies experience abnormal power-down
Solution Approach 1:
The patent implements feedback by using monitoring circuits to detect power-down conditions and feed this information back to the control circuit. This feedback mechanism allows the system to respond to abnormal power-down conditions while maintaining control over the shutdown sequence, resolving the contradiction between fast voltage drop and reliable shutdown execution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents output voltage overshoot and component damage by ensuring rapid and controlled power-down sequences, maintaining the enable signal low and isolating signals to prevent interference, thus enhancing server reliability during abnormal power-downs.
Implementation Method 1
an energy storage circuit, wherein an output end of the energy storage circuit is connected to the control/isolation circuit to provide reserve power for operation of the two-stage MOS transistors of the control/isolation circuit
Implementation Method 2
the control/isolation circuit controls and isolates an output signal of the signal indication circuit by means of two-stage Metal-Oxide-Semiconductor (MOS) transistors
Data Source
AI summary
The control circuit includes a signal indication circuit, a control/isolation circuit, and an energy storage circuit; the signal indication circuit is a logic AND gate circuit, has an input end connected to multiple paths of power-down monitoring signals and an output end connected to an input end of the control/isolation circuit, and when a level of any path of power-down monitoring signal is low, outputs a low level to the control/isolation circuit; an output end of the control/isolation circuit is connected to an enable end of a Direct Current (DC) power chip, and the control/isolation circuit controls and isolates an output signal of the signal indication circuit by means of two-stage Metal-Oxide-Semiconductor (MOS) transistors; and an output end of the energy storage circuit is connected to the control/isolation circuit to provide reserve power for operation of the MOS transistors of the control/isolation circuit.