Sequential CFET Wafer Bonding With Backside Power Rails
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors to smaller sizes due to limitations in two-dimensional (2D) circuit designs, particularly in forming three-dimensional (3D) stacked transistors with efficient power delivery and signal wiring, which leads to increased parasitic resistance and complexity in integrating backside power and signal lines.
Innovation Solution
A method involving the bonding of wafers with alternating epitaxial layers to form stacked transistors, where backside power rails and signal wiring are integrated through a bonding dielectric layer, allowing for wider power rails and improved connectivity by removing residual FIN structures, thereby reducing parasitic resistance and enabling more flexible wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional circuit designs are used with traditional wiring above active devices, then manufacturing process is simpler, but transistor density and area scaling are limited
Solution Approach 1:
The patent implements three-dimensional stacked transistor architecture where multiple tiers of transistors are vertically stacked above each other on the same substrate area. This transitions from traditional two-dimensional planar circuits to three-dimensional vertical stacking, dramatically increasing transistor density per unit area while managing complexity through systematic interconnect structures
2Reliability
If backside power distribution network is integrated through bonding dielectric layer, then parasitic resistance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The bonding dielectric layer is formed on the substrate before the active devices are fabricated. Power rails are subsequently formed on the backside of the substrate, making contact with the pre-formed bonding dielectric layer. This preliminary positioning of the bonding dielectric enables efficient backside power distribution while managing manufacturing complexity through staged processing
3Reliability
If wider power rails are formed through removal of residual FIN structures, then electrical conductivity is improved, but structural integrity challenges arise
Solution Approach 1:
Residual FIN structures that obstruct the formation of wide power rails are selectively removed from the substrate. This extraction of obstructive elements enables the formation of continuous, wide-power rails with low parasitic resistance while maintaining structural integrity through selective removal rather than aggressive processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density and reduces parasitic resistance by allowing wider power rails and improved connectivity, facilitating the integration of backside power and signal wiring, which is crucial for advanced semiconductor devices like CFETs, enabling better performance and area scaling.
Implementation Method 1
bonding a first wafer to a second wafer via a first bonding dielectric layer
Implementation Method 2
a first stack of alternating layers of epitaxially grown semiconductor layers formed over a second bulk semiconductor material
Data Source
AI summary
A semiconductor device includes backside power rails over a bulk semiconductor material, a first bonding dielectric layer over the backside power rails, a first tier of transistors over the first bonding dielectric layer, a second bonding dielectric layer over the first tier of transistors, and a second tier of transistors over the second bonding dielectric layer. The first tier of transistors includes first channel structures having a first epitaxially grown semiconductor material. The second tier of transistors includes second channel structures having a second epitaxially grown semiconductor material. The backside power rails are spaced apart from the first tier of transistors by the first bonding dielectric layer. The first tier of transistors is spaced apart from the second tier of transistors by the second bonding dielectric layer.