Sequential Circuit Error Detection With a Time Borrowing Latch
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Solution Overview
Problem
Conventional sequential circuits with error detection are costly in terms of clock energy consumption and susceptible to datapath metastability issues, leading to unnecessary clock frequency limitations and potential undetected timing errors.
Innovation Solution
The introduction of a transition detector with a time borrowing latch (TDTB) in sequential circuits, which detects late transitions and initiates error correction, reducing clock energy consumption and eliminating datapath metastability by ensuring data resolution during clock transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection circuitry (latch and XOR gate) is employed to detect late transitions, then error detection capability is improved, but clock energy consumption increases
Solution Approach 1:
The patent extracts the error detection function from the conventional latch-XOR structure and implements it through a metastability detector that specifically monitors for metastable conditions. This selective extraction maintains error detection capability while reducing the energy overhead associated with continuous latch operation and XOR gate comparisons.
Solution Approach 2:
The patent introduces a metastability detector as an intermediary component between the sequential element and the error detection logic. This mediator specifically identifies metastable transitions, enabling error detection to trigger only when actually needed, thereby reducing unnecessary energy consumption compared to continuous monitoring approaches.
2Reliability
If conventional error detection circuitry is used, then error detection is achieved, but datapath metastability issues remain and design overhead increases
Solution Approach 1:
The patent extracts the metastability detection function as a separate, dedicated component. By taking out this specific function from the general error detection circuitry, the design achieves targeted metastability handling without the overhead of comprehensive error detection circuits, reducing overall device complexity.
Solution Approach 2:
The metastability detector is positioned to detect metastable conditions at the point they occur, before they can propagate through the datapath. This preliminary detection and handling prevents metastability issues from affecting downstream logic, eliminating the need for additional complexity elsewhere in the design.
3Reliability
If timing guardbands are increased to account for dynamic variations, then timing reliability is improved, but clock frequency is unnecessarily limited
Solution Approach 1:
The patent implements feedback through the metastability detector that monitors actual timing violations and triggers error correction only when needed. This feedback mechanism allows the system to operate at higher clock frequencies without timing guardbands, as the feedback-driven error correction compensates for dynamic variations on-demand rather than requiring conservative frequency limitations.
Data Source
AI summary
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.