Sequential Prediction Circuit for Return-Target Instruction Fetching
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Solution Overview
Problem
Existing processor circuits waste bandwidth and power due to indiscriminate instruction fetching for return instructions, as next fetch predictor circuits fail to predict fetch width and bank indicators for target addresses of return instructions.
Innovation Solution
Implementing a return prediction circuit that tracks fetch parameters for return instructions, including a return address stack circuit and a fetch control circuit to manage fetch operations efficiently, thereby reducing unnecessary instruction fetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If next fetch predictor circuits are used to retrieve fetch groups, then instruction fetch capability is improved, but bandwidth and power are wasted due to indiscriminate fetching for return instructions
Solution Approach 1:
The sequential prediction circuit performs preliminary analysis of sequential fetch addresses before actual instruction fetching occurs. By predicting fetch parameters (fetch width and bank indicators) in advance for sequential addresses, the system avoids indiscriminate fetching and reduces bandwidth and power consumption while maintaining improved instruction fetch capability.
2Measurement precision
If fetch parameters are stored for all fetched instructions, then prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The sequential prediction circuit implements local quality by specializing in predicting parameters only for sequential fetch addresses, while other prediction circuits handle different address types. This division of labor improves prediction accuracy for sequential addresses without requiring the entire system to become more complex, as each circuit has a focused, simplified function.
Data Source
AI summary
An apparatus includes a sequential fetch circuit configured to provide a given sequential fetch address for use in a fetch request, and a sequential prediction circuit configured to store, for one or more sequential fetch addresses, respective sets of sequential fetch parameters for use in subsequent fetch requests. The apparatus further includes a fetch control circuit configured to, based at least on retrieving a particular sequential fetch address from the sequential fetch circuit, use the particular sequential fetch address to determine whether a particular set of sequential fetch parameters exists in the sequential prediction circuit. The fetch control circuit is also configured to, based at least on a determination that the particular set of sequential fetch parameters exists, use the particular set of sequential fetch parameters to create a next fetch request to retrieve instructions starting at the particular sequential fetch address.