Sequential Memory Cell Programming and Verification
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Solution Overview
Problem
Conventional memory devices face challenges in meeting specific timing margins and power consumption preferences, particularly in applications requiring efficient write operations across multiple memory cells.
Innovation Solution
The memory device employs a method involving sequential programming of multiple memory cells in a write stage followed by a write verify stage, using controlled voltage levels and select transistors to ensure target states are reached, thereby optimizing programming time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential programming is performed on multiple memory cells in conventional memory devices, then programming completeness is ensured, but programming time and power consumption increase
Solution Approach 1:
The patent segments the programming process into distinct stages: a first programming stage that programs a first subset of memory cells, and a second programming stage that programs a second subset of memory cells. This segmentation allows parallel or sequential execution of programming operations on different cell subsets, reducing total programming time while ensuring all cells are programmed. The segmentation also enables intermediate verification points between stages.
Solution Approach 2:
The patent performs preliminary programming of a first subset of memory cells before completing programming of the second subset. This preliminary action allows the system to start programming operations early and use the intermediate state for verification or partial completion strategies, reducing the overall time required while maintaining programming reliability.
2Reliability
If sequential programming is performed on multiple memory cells in conventional memory devices, then programming completeness is ensured, but power consumption increases
Solution Approach 1:
The patent divides the memory cell population into multiple subsets that are programmed in separate stages. This segmentation allows power management circuits to control voltage supply to different subsets independently, reducing peak power consumption. The first subset is programmed with first voltage levels, and the second subset is programmed with second voltage levels, allowing power to be distributed over time rather than simultaneously to all cells.
Solution Approach 2:
The patent employs periodic programming actions with distinct voltage levels applied at different times. The first voltage levels are applied during a first time period for the first subset, and second voltage levels are applied during a second time period for the second subset. This periodic action pattern reduces instantaneous power consumption while ensuring all cells receive necessary programming voltage sequences.
3Loss of time
If multiple memory cells are programmed simultaneously, then programming time is reduced, but timing margin requirements become more difficult to meet
Solution Approach 1:
The patent segments the memory cell programming into ordered subsets with defined timing relationships. The first subset is programmed with established timing margins, and the second subset is programmed subsequently with controlled timing. This segmentation maintains precise timing control for each subset while achieving overall time reduction through parallel or pipelined execution of stages.
Solution Approach 2:
The patent performs preliminary programming of the first subset with well-defined timing margins before proceeding to the second subset. This preliminary action establishes a timing foundation that ensures manufacturing precision requirements are met for critical cells, while subsequent programming of the second subset can be optimized for speed without compromising overall timing margins.
4Speed
If higher voltage levels are applied for faster programming, then programming speed increases, but power consumption and reliability risks increase
Solution Approach 1:
The patent applies voltage levels periodically in distinct programming stages. First voltage levels are applied during a first time period for the first subset, and second voltage levels are applied during a second time period for the second subset. This periodic voltage application achieves fast programming where needed while reducing average power consumption through controlled voltage timing and duration.
Solution Approach 2:
The patent applies different voltage levels to different subsets of memory cells based on local programming requirements. The first subset receives first voltage levels optimized for its specific characteristics, while the second subset receives second voltage levels suited to its requirements. This local quality approach ensures each cell subset is programmed at optimal speed without unnecessarily increasing power consumption across the entire memory array.
Data Source
AI summary
Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.