Sequential Circuit Output Clamping for Low-Leakage Sleep Modes
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Solution Overview
Problem
Existing data processing systems face challenges in reducing leakage power without interfering with clocking paths or critical pathways, and current methods for minimizing leakage power in low power modes are energy and time expensive.
Innovation Solution
The introduction of a clamp signal input to sequential circuitry that allows the data output to be clamped to a forced value, reducing leakage power in combinatorial circuitry without affecting clocking paths or critical pathways, and the use of additional circuitry to select optimal output values for low power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system enters a halted mode with clock switched off to reduce power consumption, then power efficiency is improved, but leakage power in combinatorial logic becomes highly state dependent and cannot be minimized
Solution Approach 1:
The invention changes the state parameters of sequential circuitry outputs during halted mode by introducing a clamp signal that forces outputs to specific values (0 or 1). This parameter change minimizes leakage power in combinatorial logic by ensuring outputs are in low-leakage states, directly addressing the state-dependent leakage problem while maintaining the halted mode's power efficiency benefits
2Loss of energy
If standard algorithms are used to calculate minimum leakage vectors and scan in state bits to produce optimal low-leakage state, then leakage power is minimized, but energy and time consumption increases significantly
Solution Approach 1:
The clamp signal mechanism performs preliminary action by directly forcing sequential circuitry outputs to predetermined low-leakage values when halted mode is detected, bypassing the need for complex algorithms and iterative scanning processes. This eliminates the time-consuming state establishment phase while achieving the same leakage minimization goal
Solution Approach 2:
The invention extracts the essential function of achieving low-leakage states from the complex algorithmic approach, isolating only the critical action of forcing outputs to specific values. This simplification removes unnecessary computational overhead and time consumption while retaining the core benefit of leakage minimization
3Loss of energy
If existing sequential circuitry is modified to add clamp signal input and forced value output capability, then leakage power reduction is achieved, but device complexity increases
Solution Approach 1:
The clamp signal input is designed to be universally applicable to sequential circuitry outputs, allowing a single additional input structure to serve multiple functions: normal operation mode and halted mode with leakage minimization. This multi-functionality approach reduces overall complexity compared to implementing separate dedicated circuits for different operational states
Data Source
AI summary
Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal.