SerDes Chiplet Architecture for Heat Isolation and Cost Reduction
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Solution Overview
Problem
Existing SerDes technologies face challenges in efficiency, cost, performance, and heat management, particularly due to the integration of analog and digital components in a single chip or chiplet, which limits scalability and increases development costs.
Innovation Solution
The proposed solution involves embedding the digital signal processor (DSP) in a digital-core die with a smaller technology-node geometry and the analog front end (AFE) in a separate chiplet, allowing for sequential de-serializing and serializing processes. This separation enables efficient processing in both digital and analog domains while isolating heat generated by the AFE from the DSP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If analog front end (AFE) and digital signal processor (DSP) are integrated in a single chip or chiplet, then device complexity is reduced, but heat management deteriorates and manufacturing precision requirements increase
Solution Approach 1:
The patent divides the SerDes device into two separate components: an analog front end (AFE) chiplet and a digital signal processor (DSP) die. The AFE handles analog signal processing while the DSP handles digital processing, physically separating heat-generating analog circuits from sensitive digital circuits. This segmentation resolves the contradiction by maintaining functional integration benefits while enabling independent thermal management for each component.
2Ease of manufacture
If AFE and DSP are manufactured using the same technology-node geometry, then manufacturing process is simplified, but manufacturing precision and performance optimization are compromised
Solution Approach 1:
The patent enables different technology-node geometries for the AFE chiplet and DSP die. The DSP can be manufactured using more advanced, smaller technology nodes for higher performance, while the AFE can use older, more cost-effective technology nodes. This segmentation allows each component to be optimized independently for its specific performance and cost requirements without constraining the other.
Solution Approach 2:
The patent applies different manufacturing quality standards and technology nodes to different parts of the system. The DSP die uses advanced technology-node geometry for high-performance digital processing, while the AFE chiplet uses older technology nodes suitable for analog processing. This local quality approach allows each component to be manufactured with the appropriate level of precision and technology for its specific function.
3Productivity
If advanced technology-node geometry is used for digital processing, then processing efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The patent separates the digital processing function (DSP) from analog processing (AFE), allowing the DSP to be manufactured using advanced technology-node geometry for high processing efficiency, while the AFE can be manufactured using older, more cost-effective technology nodes. This segmentation enables selective application of advanced manufacturing only where performance is critical.
4Reliability
If AFE and DSP are separated into different chiplets and dies, then heat interference is reduced and performance is improved, but device complexity and interconnection requirements increase
Solution Approach 1:
The patent introduces a parallel digital interface as an intermediary connection between the AFE chiplet and DSP die. This interface enables high-speed data transfer while maintaining physical separation of the components. The intermediary connection resolves the contradiction by providing a controlled, optimized communication path that manages the complexity of inter-chiplet/die communication while enabling performance benefits of separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement improves processing efficiency, reduces heat interference, and lowers development and manufacturing costs by utilizing more advanced technology for digital processing and older, cheaper technology for analog components, thus enhancing the overall performance and scalability of SerDes systems.
Implementation Method 1
converting, by the receiver, the received analog signal into a digital signal
Implementation Method 2
converting, by a transmitter of an AFE connected to the DSP through a parallel digital interface, the processed digital signal into an analog signal
Data Source
AI summary
De-serializing and serializing methods are disclosed for data transmission between chips involving an arrangement of an analog frond end and a digital signal processor for the de-serializing and serializing methods. According to the present disclosure, processing in the digital domain may be carried out by a chip with smaller technology-node geometry while processing in the analog domain may be carried out by a chiplet suitable for analog components. Heat generated by the AFE is isolated from the DSP. Furthermore, costs associated with development and manufacturing may be lowered.