SerDes Clock Network with Divided PLL Outputs for FPGA Logic
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Solution Overview
Problem
Current SerDes module clock network architectures limit the independent use of PLL resources, as they are tied to internal channels and cannot generate multiple clocks for FPGA applications, leading to resource wastage when the SerDes function is not used.
Innovation Solution
A SerDes module clock network architecture featuring a reference clock input port, data transmission channels, user logic interfaces, and frequency division branches, where the PLL output clock is distributed to multiple user logic interfaces via independent frequency division branches, allowing for flexible clock output to FPGA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL is dedicated to the internal channel of SerDes, then the clock signal is stable and reliable for data transmission, but the PLL cannot be used independently for other FPGA clock requirements, resulting in resource waste
Solution Approach 1:
The PLL module is designed to serve multiple functions: it can provide clock signals for the SerDes internal channel and simultaneously provide independent clock outputs for other FPGA logic through frequency division branches. This multi-functionality allows the same PLL resource to be shared across different applications without requiring additional dedicated PLLs for each function.
Solution Approach 2:
The clock network is segmented into multiple independent frequency division branches, each capable of independently dividing the PLL output clock and providing it to different user logic interfaces. This segmentation allows the clock distribution system to serve multiple purposes while maintaining the integrity of the original SerDes channel connection.
2Device complexity
If the PLL is tied to the SerDes internal channel, then the architecture is simple and easy to implement, but multiple PLLs cannot be used to generate multiple clocks when SerDes function is not used
Solution Approach 1:
The PLL module is designed to serve multiple functions: it can provide clock signals for the SerDes internal channel and simultaneously provide independent clock outputs for other FPGA logic through frequency division branches. This multi-functionality allows the same PLL resource to be shared across different applications without requiring additional dedicated PLLs for each function.
Solution Approach 2:
The frequency division branches are dynamically configurable, allowing the system to adapt between different operating modes: when SerDes is active, the PLL serves the channel; when SerDes is inactive, the same PLL can independently generate multiple clocks for other FPGA functions. The configurable frequency division ratios enable flexible adaptation to different clock requirements.
3Adaptability or versatility
If frequency division branches are added to the clock network, then multiple clock outputs can be provided to user logic interfaces, but the device complexity increases
Solution Approach 1:
The clock network is segmented into multiple independent frequency division branches, each capable of independently dividing the PLL output clock and providing it to different user logic interfaces. This segmentation allows the clock distribution system to serve multiple purposes while maintaining the integrity of the original SerDes channel connection.
Solution Approach 2:
The frequency division functionality is merged into the existing SerDes clock network architecture rather than being implemented as separate external circuits. By integrating the frequency division branches within the SerDes module, the patent reduces overall system complexity while still achieving multiple independent clock outputs for FPGA logic.
Data Source
AI summary
A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.