SerDes Multi-Mode DFE With Constrained ISI Threshold Selection
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Solution Overview
Problem
Current decision feedback equalizer (DFE) implementations face challenges in high-speed digital communication due to the need for fast comparators, which increase power requirements and are infeasible with current silicon semiconductor processing technologies, especially as symbol intervals shrink.
Innovation Solution
A SerDes receiver design incorporating a front-end filter, precomputation unit, and controller that converts receive signals into linearly-equalized signals using a set of comparators with threshold values dependent on post-cursor inter-symbol interference (ISI) values, with the controller constraining these values based on channel loss to optimize symbol decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precomputation modules are used to combat ISI in high-speed DFE, then equalization performance is improved, but the number of fast comparators increases greatly, leading to increased power requirements
Solution Approach 1:
The patent segments the equalization process into distinct stages: linear equalization followed by decision feedback equalization. This segmentation allows each stage to use optimized techniques appropriate to its function, reducing the overall computational burden and power requirements while maintaining equalization effectiveness.
Solution Approach 2:
The patent applies preliminary linear equalization to pre-process the received signal before the decision feedback stage. This preliminary action reduces the ISI burden on the subsequent DFE comparators, allowing them to operate with fewer resources while achieving the same overall equalization performance.
2Speed
If the number of fast comparators is increased to handle high-speed signaling, then equalization capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the high-speed equalization task into two parts: a linear equalizer handling initial signal conditioning and a DFE handling residual ISI. This segmentation reduces the speed and complexity requirements of individual comparator circuits while maintaining overall high-speed capability.
Solution Approach 2:
The patent employs adaptive decision thresholds in the DFE that are adjusted based on detected signal conditions and ISI characteristics. This dynamic adaptation allows the system to maintain high-speed performance with fewer comparators by optimizing their operation for current channel conditions rather than over-provisioning for all possible scenarios.
Data Source
AI summary
An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F1 if the receive signal uses a PAM4 signal constellation, setting F1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.