SERDES Hybrid Clocking for Multiphase Timing and Lower Power
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Solution Overview
Problem
Existing clock and data recovery circuits in high-speed serial buses face challenges with increased power consumption and phase relationship variations leading to data errors, necessitating improved clock generation and calibration techniques.
Innovation Solution
A hybrid clock generation circuit that includes dividers, delay cells, and multiplexers to produce multi-phase clock signals, allowing for both full-rate and half-rate operations, reducing power consumption and improving phase accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple high-frequency clock signals are used to control SERDES operations, then timing control and data transmission speed are improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action by using a single continuous-clock signal that is periodically divided into multiple phase-shifted clock signals (e.g., 0°, 90°, 180°, 270° phases) through divider circuits. This periodic generation of multi-phase clocks from a single source allows the SERDES to operate at high speeds for data transmission while the power consumption remains tied to a single clock source rather than multiple independent high-frequency clocks, thus resolving the contradiction between speed and power consumption.
2Measurement precision
If multiple clock signals with different phases are generated, then timing control precision is improved, but phase relationship variations and data errors increase
Solution Approach 1:
The patent implements feedback through a phase detector that continuously monitors the phase relationships between the generated clock signals and the incoming data stream. The phase detector compares the phase of the recovered clock with reference clocks and generates error signals that are fed back to adjust the phase alignment. This closed-loop feedback mechanism ensures that even though multiple phase-shifted clocks are generated, their phase relationships remain precise and stable, preventing data errors and maintaining high timing control precision simultaneously.
Solution Approach 2:
The patent uses an intermediary mechanism in the form of a phase-locked loop (PLL) that acts as a mediator between the single continuous-clock input and the multiple phase-shifted output clocks. The PLL ensures that all generated clock signals maintain precise phase relationships by using the input clock as a reference and adjusting the phases of derived clocks accordingly. This intermediary control structure prevents phase drift and maintains reliability while achieving the needed timing precision.
3Use of energy by moving object
If a single continuous-clock signal is used, then power consumption is reduced, but the ability to provide multi-phase clocks for high-speed operation is limited
Solution Approach 1:
The patent applies segmentation by taking a single continuous-clock signal and dividing it into multiple segmental clock signals with different phases using separate divider circuits (e.g., divide-by-2, divide-by-4 circuits). Each divider circuit generates a specific phase version of the clock, creating segmented time references from the unified clock source. This segmentation enables the system to generate the necessary multi-phase clocks for high-speed SERDES operation while maintaining power efficiency by using only one primary clock source.
Solution Approach 2:
The single continuous-clock signal serves multiple functions simultaneously: it provides the timing reference for the entire SERDES operation, serves as the input to multiple divider circuits to generate various phase-shifted clocks, and acts as the master synchronizing signal for data sampling and transmission. This multi-functionality allows the system to achieve high-speed operation with multi-phase clocks while consuming power equivalent to a single clock source, resolving the contradiction between versatility and power consumption.
Data Source
AI summary
A method for generating clock signals includes dividing an input clock signal to obtain a first in-phase output clock signal, dividing an inverted version of the input clock signal to obtain a first quadrature output clock signal, delaying edges in the input clock signal to obtain a second quadrature output clock signal, selecting a full-rate output to provide a multiphase output clock in a first mode of operation, and selecting a half-rate output to provide the multiphase output clock in a second mode of operation. The first quadrature output clock signal is a quadrature version of the first in-phase output clock signal. The first in-phase output clock signal and the first quadrature output clock signal are included in the full-rate output. The second quadrature output clock signal is included in the half-rate output and is a quadrature version of the input clock signal.