SERDES Package Layout With Shared Power Grid for Smaller Footprint
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing serializer/deserializer (SERDES) circuits for automotive and industrial applications have high circuitry costs and complexity due to large footprints and require extensive supporting circuitry, which is undesirable for multimedia distribution systems like In-Vehicle Infotainment (IVI) and Advanced driver-assistance systems (ADAS).
Innovation Solution
The integrated circuit includes a die with a mixed-signal block layout that involves a die with aligned blocks, standardized contact spacing, power distribution tiles, and capacitor elements to optimize space usage, reducing pin counts and chip size through grid sharing, resistor alignment, and efficient power supply distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SERDES circuit packaging is used, then the circuit can provide stable signal transmission, but the footprint area and supporting circuitry size increase, leading to higher cost and complexity
Solution Approach 1:
The chip is divided into multiple functional blocks (analog block, digital block, RF block, memory block) arranged in a segmented layout. Each block is independently optimized for its function, allowing efficient space utilization while maintaining signal integrity through dedicated power and ground networks for each segment.
Solution Approach 2:
Multiple power domains (VDD_ANA, VDD_DIG, VDD_RF, VDD_MEM) and ground networks are merged into a unified power distribution system with shared power rails and ground references. This consolidation reduces the overall power network footprint while maintaining stable voltage levels across all functional blocks.
2Reliability
If traditional SERDES circuit packaging is used, then the circuit can provide stable signal transmission, but the supporting circuitry complexity increases, leading to higher cost
Solution Approach 1:
The power distribution network is designed as a universal infrastructure that serves all functional blocks simultaneously. Shared power rails, ground networks, and decoupling capacitor arrays provide power and signal stability across analog, digital, RF, and memory blocks through a single unified system, reducing the need for separate supporting circuitry for each block.
Solution Approach 2:
The layout parameters of power and ground networks are optimized to change with functional requirements. Power rail widths, ground network densities, and capacitor placements are adjusted based on the specific power and signal needs of each functional block, allowing the supporting circuitry to adapt its complexity rather than maintaining fixed high complexity throughout.
3Ease of manufacture
If larger chip footprint is used, then more space is available for power distribution and signal routing, but the overall cost and packaging size increase
Solution Approach 1:
The power distribution system utilizes three-dimensional routing with multiple metal layers. Power rails and ground networks are distributed across different vertical layers, allowing complex power and signal routing to be achieved within a compact two-dimensional footprint by exploiting the third dimension for routing complexity.
Solution Approach 2:
Functional blocks are nested within the chip layout with smaller blocks positioned within or adjacent to larger blocks. The analog block, digital block, RF block, and memory block are arranged in a nested configuration that maximizes space utilization while maintaining adequate spacing for power distribution and signal routing pathways.
Data Source
AI summary
An integrated circuit may include a die. An integrated circuit may include a plurality of mixed-signal blocks aligned and coupled with a block grid and having dimensions corresponding to chip dimensions by a common integer factor. An integrated circuit may include a diffusion element having a grid length dimension with a fixed and standardized contact spacing. An integrated circuit may include a power distribution system comprising. An integrated circuit may include one or more tiles with tile dimensions related to the block grid by a common integer factor; and internal tracks configured to provide distribution of a plurality of power supplies in each direction. An integrated circuit may include a set of capacitor elements aligned with the block grid and configured to enable efficient utilization of space between the plurality of mixed-signal blocks.