Serial Array Memory Transistor Architecture with Gate Isolation
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Solution Overview
Problem
Conventional NAND memory transistors suffer from high read latency due to high capacitance metal bitlines and high resistance strings, which slows down read operations in semiconductor memory devices.
Innovation Solution
A serial array memory transistor architecture is introduced, utilizing NAND or NAND-type memory transistors with a discrete pass transistor having small capacitance, which modulates current flow or voltage at an adjacent metal bitline to sense program or erase states, significantly reducing read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional NAND memory transistors are used with high capacitance metal bitlines, then data storage capacity is maintained, but read latency increases significantly
Solution Approach 1:
The patent extracts the high-capacitance metal bitline from the read path and replaces it with a low-capacitance semiconductor bitline. This separation allows the metal bitline to be used only for programming/erasing operations while the semiconductor bitline handles high-speed read operations, thereby reducing read latency without affecting storage capacity.
Solution Approach 2:
The patent changes the bit capacitance parameter by transitioning from high-capacitance metal bitlines to low-capacitance semiconductor bitlines. This parameter change directly reduces the time constant (τ = RC) for read operations, enabling faster read speeds while maintaining data storage functionality.
2Productivity
If high capacitance metal bitlines are used for data storage, then storage capacity is maintained, but read operation speed decreases
Solution Approach 1:
The patent extracts the high-capacitance metal bitline from the read path and replaces it with a low-capacitance semiconductor bitline. This separation allows the metal bitline to be used only for programming/erasing operations while the semiconductor bitline handles high-speed read operations, thereby reducing read latency without affecting storage capacity.
Solution Approach 2:
The patent changes the bit capacitance parameter by transitioning from high-capacitance metal bitlines to low-capacitance semiconductor bitlines. This parameter change directly reduces the time constant (τ = RC) for read operations, enabling faster read speeds while maintaining data storage functionality.
3Ease of manufacture
If conventional serial array memory architecture is used, then manufacturing simplicity is maintained, but read latency remains high
Solution Approach 1:
The patent changes the bitline material parameter from metal to semiconductor, which fundamentally alters the capacitance characteristic. This parameter change enables low-latency read operations while the overall serial array architecture remains intact, preserving manufacturing simplicity.
Solution Approach 2:
The patent segments the bitline functionality into two separate lines: metal bitlines for programming/erasing and semiconductor bitlines for reading. This segmentation resolves the contradiction by allowing each bitline type to optimize for its specific function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in read speeds that are orders of magnitude faster than conventional NAND memory, while maintaining optimal program and erase times, and allows for higher transistor density without increasing the size of the amplifier region.
Implementation Method 1
The discrete transistor gate modulates current flow or voltage at an adjacent metal bitline
Data Source
AI summary
Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.