Serial CMOS Decoder Using Low-Voltage MOS for High-Voltage Output
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Solution Overview
Problem
Current non-volatile memory word line decoding circuits require high-voltage transistors to manage high-voltage operations, leading to increased device area, complexity, and reduced reliability due to the need for multiple large high-voltage components.
Innovation Solution
A decoding circuit utilizing two CMOS inverters connected serially with four switches, where the source and substrate of PMOS and NMOS transistors are strategically connected and switched to manage high-voltage operations using low-voltage MOS transistors, allowing for high-voltage output while maintaining a simple and reliable design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage transistors are used to manage high-voltage operations, then high-voltage functionality is achieved, but device area increases and reliability decreases
Solution Approach 1:
The patent changes the voltage parameters applied to different terminals of the same low-voltage MOS transistor. By applying high voltage to the substrate terminal while maintaining low voltage at the gate and source terminals, the transistor can withstand high voltage stress without requiring high-voltage transistor structures. This parameter transformation allows low-voltage transistors to perform high-voltage functions, improving reliability while maintaining high-voltage capability.
2Adaptability or versatility
If high-voltage transistors are used to manage high-voltage operations, then high-voltage output is achieved, but device area increases
Solution Approach 1:
The patent transforms the voltage distribution parameters across transistor terminals to enable low-voltage MOS transistors to output high voltages. By connecting transistors in series configurations and applying appropriate voltage divisions (e.g., VCC/2 at intermediate nodes, VCC at output), the circuit achieves high-voltage output capability using small low-voltage transistors, thereby reducing device area while maintaining high-voltage functionality.
Solution Approach 2:
The patent segments the high-voltage output function across multiple low-voltage transistors connected in series. Instead of using a single large high-voltage transistor, the total voltage is divided and applied to different terminals of smaller transistors (e.g., substrate of one transistor, source of another), allowing the system to achieve high-voltage output through coordinated operation of multiple small components, thus reducing overall device area.
3Adaptability or versatility
If multiple high-voltage transistors are used, then high-voltage operations are supported, but circuit complexity increases
Solution Approach 1:
The patent makes low-voltage MOS transistors multi-functional by enabling them to operate in both low-voltage mode (for fast decoding) and high-voltage mode (for programming/erasing operations). The same transistors serve different functions by changing their terminal voltage configurations, eliminating the need for separate high-voltage transistor circuits and thereby reducing overall circuit complexity while maintaining full operational versatility.
Solution Approach 2:
The patent uses parameter changes (voltage level transformations) to enable a single low-voltage transistor circuit to support both low-voltage and high-voltage operations. By dynamically adjusting which terminals receive high voltage versus low voltage, the same hardware infrastructure handles multiple voltage regimes, simplifying the circuit architecture compared to having separate dedicated circuits for each voltage level.
4Area of stationary object
If low-voltage MOS transistors are used for high-voltage operations, then device area is reduced, but voltage withstanding capability must be enhanced
Solution Approach 1:
The patent enhances the voltage withstanding capability of low-voltage MOS transistors by changing the voltage parameters applied to their terminals. Instead of requiring the transistor channel to withstand high voltage directly, the patent applies high voltage to the substrate terminal while keeping the gate-source voltage within low-voltage limits. This parameter transformation allows the transistor to withstand high voltages through its substrate tolerance rather than requiring high-voltage channel design, thereby maintaining small device area while achieving high voltage withstanding capability.
Data Source
AI summary
A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage.