Digital Serial Link Receiver with Single-Oscillator Low-Jitter Clock Recovery
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Solution Overview
Problem
Existing serial link receivers require two oscillators to effectively regenerate a low jitter clock, which is inefficient and costly in terms of hardware implementation.
Innovation Solution
A serial link receiver apparatus and method that regenerates a low jitter clock using only one oscillator, comprising a phase lock loop, binary phase detector, digital clock-data recovery filter, phase rotators, and low pass filter, to perform clock-data recovery and phase rotation, thereby reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two oscillators are used to regenerate low jitter clock, then clock quality is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of two separate oscillators into a single oscillator system. The first oscillator generates a clock signal that is then processed through phase rotation and filtering stages to produce the final low-jitter recovered clock, eliminating the need for a second oscillator while maintaining clock quality.
Solution Approach 2:
The single oscillator in the patent performs multiple functions: it generates the initial clock signal, and through the phase rotation and filtering mechanism, it also produces the low-jitter recovered clock that would traditionally require a separate oscillator. This multi-functional approach reduces hardware complexity while maintaining reliability.
2Measurement precision
If two oscillators are used to regenerate low jitter clock, then timing tracking accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the timing tracking function with the single oscillator output by implementing phase rotation based on control words derived from the phase error signal. This allows one oscillator to achieve the timing tracking accuracy previously requiring two oscillators, thereby reducing manufacturing cost.
Solution Approach 2:
The patent changes the phase parameter of the oscillator output through controlled phase rotation. By adjusting the phase of the clock signal based on the control word (which is derived from the phase error), the system achieves accurate timing tracking with a single oscillator, reducing component count and manufacturing cost.
3Reliability
If PLL filtering is applied to reduce clock jitter, then clock cleanliness is improved, but response speed to timing changes decreases
Solution Approach 1:
The patent applies preliminary phase rotation to the oscillator output based on the control word before the final clock is used for data recovery. This pre-adjustment of phase allows the system to respond more quickly to timing changes while the low-pass filter continues to clean the clock signal, effectively decoupling the response speed from the filtering operation.
Solution Approach 2:
The patent introduces dynamic phase rotation that can adaptively adjust the clock phase in response to timing changes in the input signal. This dynamic adjustment allows the system to maintain fast response to timing changes while the low-pass filter operates to clean the clock signal, resolving the contradiction between filter cleanliness and response speed.
Data Source
AI summary
An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.