Serial Memory Link Coding With 17B/20B Low-Latency Run-Length Control

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Solution Overview

Problem

Conventional data communication coding techniques, such as 8 B/10 B coding, introduce high latency in memory systems using high-speed serial links, which is undesirable, especially in mobile devices where memory performance is critical and DC balancing is not necessary.

Innovation Solution

A 17 B/20 B coding system is employed that maintains a maximum run length of 5 bits or less, allowing for efficient encoding and decoding without the need for DC balancing, thereby reducing latency and improving memory performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If 8 B/10 B coding is used to guarantee DC-balanced output and maximum run length, then reliability is improved, but latency increases significantly

Engineering Contradiction:
Improvebit error rateVSAvoidcoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The 17 B/20 B coding system segments the data into smaller code blocks that are processed independently, eliminating the need for cascaded calculations across entire bytes. This segmentation allows parallel processing of multiple code blocks simultaneously, reducing overall latency while maintaining run length constraints for reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the coding parameters from 8 B/10 B to 17 B/20 B, adjusting the code rate and structure to better suit memory system requirements. This parameter change enables lower latency operation while maintaining the necessary run length properties for reliable detection in AC-coupled serial links

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If 8 B/10 B coding is used to provide DC-balanced output, then compatibility with AC-coupling is improved, but device complexity increases

Engineering Contradiction:
ImproveAC-coupling compatibilityVSAvoidcoding system complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The invention extracts and removes the DC-balancing requirement from the coding system, recognizing that memory systems using high-speed serial links do not need AC-coupling compatibility. This extraction simplifies the coding system by eliminating DC-balancing constraints while retaining essential run length limitations for reliable signal detection

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of forcing the coding system to adapt to AC-coupling requirements (DC-balancing), the invention inverts the approach by designing the coding system independently of AC-coupling constraints. This inversion simplifies the system by removing unnecessary complexity while maintaining compatibility through run length control

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If maximum run length is limited to 5 or less, then reliability is improved, but productivity decreases

Engineering Contradiction:
Improvesignal detection accuracyVSAvoidmemory performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The 17 B/20 B coding system dynamically manages run length constraints by using a larger code space that provides more flexibility in encoding. This dynamic approach allows the system to maintain run length limits for reliability while achieving higher throughput and productivity through more efficient use of the available code combinations

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7777652B2Coding system for memory systems employing high-speed serial links
Publication Date: 2010.08.17 LATTICE SEMICON CORP
  • US7777652B2 patent drawing
  • US7777652B2 patent drawing
  • US7777652B2 patent drawing

AI summary

A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.