Individual Digits Conversion TRIZ Cases
- Pseudo Differential Interconnect for Common-Mode Noise Rejection
Neighbor-signal comparison and reference voltages let single-ended interconnects reject common noise over longer distances while saving chip area.
- Chunk Signature Lookup Using Anchor Blocks for Fast Deduplication
Anchor chunks and spatial locality narrow chunk-signature searches, speeding deduplication lookups without sacrificing compression ratio.
- Block-Based Data Encoding for Zero-Free Binary String Conversion
Binary data is split into blocks and zero bytes are replaced with a block-specific marker to avoid string splitting and simplify decoding.
- Adaptive Entropy Coding with Grouped Literal Blocks
Grouping dispersed literal symbols into separate compressed blocks cuts fractional bit loss and improves adaptive entropy coding output size.
- Serial Memory Link Coding With 17B/20B Low-Latency Run-Length Control
A 17B/20B coding scheme cuts serial memory link latency while keeping run length at 5 bits or less for reliable signal detection.
- Dummy Data Preamble for DC-Balanced Link Startup Noise
A dummy-data preamble creates intermediate switching before the first DC-balanced word, cutting startup SSN while preserving clock recovery.
- Block Image Compression Mode Selection for Low-Bandwidth Decoding
Two block compression modes cut memory access and decoding effort by matching each image block to its color properties.
- History Buffer Decompression Across Local and Remote Memory
Asynchronous history-buffer fetching lets decompression continue with local data while remote dictionary pages are loaded, easing memory pressure.
- DBI Signal Generation Circuit Without Short-Circuit Current
Separate-node charge sharing and comparator detection generate DBI signals with lower current use and fewer transfer errors in memory.
- FIFO Radix Coding for Non-Power-of-2 Symbol Compression
Mixed-radix FIFO coding improves bit usage for non-power-of-2 symbols while preserving decoding order and manageable complexity.
- Duobinary Backplane Signaling for High-Speed Signal Integrity
Duobinary signaling reshapes backplane data to overcome frequency roll-off, enabling high-speed links with lower power and simpler circuits.
- Balanced DBI Coding for Low-Power Memory Refresh
By balancing zero counts in DBI-encoded refresh data, this case cuts memory refresh power and switching noise with minimal coding overhead.
- Binary Block Compression Using Combinatorial Index Encoding
Combinatorial index encoding compresses binary acknowledgement blocks with randomly distributed errors, reducing bandwidth in satellite links.
- DC-Balance Data Preamble for Simultaneous Switching Noise Reduction
Dummy-data preambles create an intermediate switching level before DC-balance words, reducing startup SSN without major speed loss.
- DC-Balanced Encoding Circuit With Fewer Signal Transitions
A DC-balanced encoding circuit cuts Manchester-style transition overhead by selectively balancing words, reducing communication energy.