Serial Scan Test Data Delivery Circuit Reducing Tester Resources
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Solution Overview
Problem
The parallel delivery method for scan test data in the integrated circuit (IC) industry requires multiple independent IO resources, leading to increased costs and complexity when testing larger devices with multiple inputs and outputs, particularly due to tight pitch trace requirements and inverse relationship with interconnection speed.
Innovation Solution
Implementing a serial delivery method for scan test data using design-for-test (DFT) circuitry within the IC, which includes a transceiver block for serial protocol conversion, a control logic block for stimulus propagation, and a Capture RAM for storing output responses, reducing the need for multiple IO resources and simplifying the test interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel delivery method is used to deliver scan test data to multiple IOs, then each IO can be tested independently with direct signal delivery, but the number of required tester resources increases significantly and interface complexity increases due to tight pitch trace requirements
Solution Approach 1:
The patent merges multiple parallel test data delivery channels into a single serial delivery channel. Instead of providing separate signal paths to each IO, the invention uses one serial interface to deliver test data that is then distributed internally to multiple IOs within the IC, reducing tester resource requirements from multiple independent channels to a single channel.
Solution Approach 2:
The patent introduces an intermediary structure within the IC (a serial interface controller and internal distribution network) that receives serial test data and redistributes it to multiple IOs. This intermediary handles the conversion from serial to parallel distribution internally, shielding the external tester from the complexity of managing multiple high-speed parallel channels.
2Speed
If parallel delivery method is used with tight pitch trace requirements, then direct signal delivery to each IO is achieved, but interconnection speed decreases due to the inverse relationship between pitch and speed
Solution Approach 1:
The patent combines multiple high-speed parallel interconnections into a single serial interconnection. By using one serial channel instead of multiple parallel channels, the invention eliminates the need for tight pitch traces between multiple high-speed signal pairs, thereby achieving high data transmission rates without the manufacturing precision constraints of tight pitch requirements.
3Device complexity
If serial delivery method is used to reduce tester resources, then fewer IO resources are required and interface complexity is reduced, but data must be converted from serial protocol and deserialized within the IC
Solution Approach 1:
The patent incorporates preliminary action by pre-configuring the IC with internal serialization/deserialization logic and routing infrastructure during the design phase. The deserialization and internal distribution capability is built into the IC architecture in advance, allowing the serial interface to operate efficiently without adding runtime overhead or compromising data transmission productivity.
Data Source
AI summary
A design for test (DFT) circuitry which delivers serial data serially is disclosed. The DFT circuit has a transceiver to receive serial data and then deserialize the serial data into deserialize data. The DFT circuit also has a control logic block which receives the deserialize data and stimulates at least one test element with the test data. The test element will generate an output response from the stimulus. The DFT circuit also has an output response block which receives the output from the test element and analyses the output response. Utilizing this DFT circuitry, a high speed data delivery method can be used for testing a device-under-test (DUT). Such method could reduce test time and the test cost associated with test process.