Serializer Transmitter Circuit for Higher Serial Signal Slew Rate
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Solution Overview
Problem
Transmitter circuits face performance reduction due to skew between clock signals, which affects the slew rate of serial signals generated by serializers.
Innovation Solution
A transmitter circuit design that includes a clock generator producing clock signals with different phases, selection circuits driven by these clock signals to selectively output parallel signals, and an output driver amplifying the signal at the output node, allowing multiple selection circuits to simultaneously drive the output node to increase the slew rate of the serial signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single selection circuit drives the output node, then the device complexity is low, but the slew rate of the serial signal is reduced
Solution Approach 1:
The invention divides the output driving function into multiple independent selection circuits (first selection circuit and second selection circuit), where each circuit drives the output node during different time periods. This segmentation allows the system to achieve higher slew rate through simultaneous driving while maintaining manageable complexity through modular design
Solution Approach 2:
The invention dynamically switches between different selection circuits based on time periods and transition signals. The first selection circuit operates during a first time period while the second selection circuit operates during a second time period, with dynamic control of which circuit actively drives the output node. This dynamic operation enables the system to optimize slew rate when needed while reducing complexity during steady-state operation
2Speed
If multiple selection circuits simultaneously drive the output node, then the slew rate of the serial signal is increased, but the device complexity increases
Solution Approach 1:
The invention merges the functionality of multiple selection circuits into a unified output driver that combines their outputs. The first and second selection circuits both connect to the same output node, and their combined driving effect produces the high slew rate serial signal. This merging approach achieves the speed improvement while consolidating the complexity into a shared output stage rather than requiring completely separate output paths
3Productivity
If selection circuits operate with skew between clock signals, then the device complexity is low, but the performance of the serializer is reduced
Solution Approach 1:
The invention uses transition signals that provide feedback information about the state of the serial signal to control the operation of selection circuits. The transition signal indicates when the serial signal changes state, and this feedback enables the selection circuits to coordinate their operation without requiring complex skew compensation mechanisms. This feedback-based control improves serializer performance while avoiding the complexity of precise clock synchronization
Data Source
AI summary
A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.