SEU-Tolerant Latch Circuit With Redundant DICE Transistor Layout
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Solution Overview
Problem
Conventional DICE circuits are vulnerable to single event upsets (SEU) when multiple OFF-state transistors across different DICE elements are simultaneously inverted due to energetic particles, leading to data inversion and malfunction.
Innovation Solution
A single event upset-tolerant latch circuit is designed by adding three redundant transistors to each of the eight transistors in the DICE circuit, forming a four-transistor circuit with serial and parallel duplications, and arranging critical transistors to reduce the likelihood of simultaneous inversion, along with a flip-flop circuit configuration using these latch circuits for enhanced SEU tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DICE circuit is used, then circuit complexity is low, but SEU tolerance is insufficient
Solution Approach 1:
The circuit is divided into multiple DICE elements (first, second, third, and fourth DICE elements) connected in a loop configuration, with each element containing critical transistors that can be independently analyzed and protected. This segmentation allows the system to tolerate SEUs in individual elements while maintaining overall functionality.
Solution Approach 2:
The patent transitions from protecting individual transistors to protecting combinations of transistors across multiple DICE elements. By requiring simultaneous inversion of three or more critical transistors across different elements to cause SEU, the protection mechanism operates at a higher dimensional level (system level rather than component level).
2Reliability
If three or more transistors are protected against simultaneous inversion, then data retention reliability is improved, but transistor arrangement complexity increases
Solution Approach 1:
The patent employs asymmetric arrangement of critical transistors within the loop configuration of DICE elements. By strategically positioning critical transistors (e.g., specific p-type and n-type transistors in alternating DICE elements) rather than symmetric distribution, the design ensures that simultaneous inversion of three or more critical transistors is statistically improbable while maintaining manageable arrangement complexity.
Data Source
AI summary
Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.