SEUP Shadow Threading for Soft Error Recovery in Processors
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Solution Overview
Problem
Unhardened processors are prone to soft errors in high-radiation environments, leading to performance degradation due to single event upsets, while radiation-hardened processors are slower and more expensive, limiting their use in high-performance applications.
Innovation Solution
Implementing a Single Event Upset Protector (SEUP) solution that uses redundant threads operating in different address spaces, with a SEUP positioned between the processor and memory and peripheral bus, caching writes and I/O operations, and restarting threads at checkpoints when mismatches occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If radiation-hardened processors are used in high-radiation environments, then reliability is improved, but performance and cost worsen
Solution Approach 1:
The patent creates a shadow copy of the processor state including registers, cache, and execution pipeline. This shadow processor runs in parallel with the primary processor, duplicating critical state elements to detect and correct soft errors without requiring the entire processor to be radiation-hardened, thus maintaining high performance while improving reliability
Solution Approach 2:
The patent introduces an intermediary error detection and correction mechanism that sits between the unhardened processor and the external environment. This intermediary layer monitors processor state, detects soft errors, and initiates rollback to checkpoint states, allowing the use of high-performance unhardened processors in radiation environments
2Reliability
If radiation-hardened processors are used in high-radiation environments, then reliability is improved, but device complexity and cost worsen
Solution Approach 1:
The patent divides the error protection function into separate modular components: checkpointing mechanisms, shadow register files, error detection logic, and rollback control. This segmentation allows the complexity to be distributed and managed independently, rather than requiring the entire processor architecture to be redesigned as radiation-hardened
Solution Approach 2:
The patent implements preliminary checkpointing where processor state is saved to stable storage at predetermined intervals before radiation-induced errors can occur. This preliminary action creates recovery points that allow the system to rollback and resume execution, reducing the need for complex real-time error correction throughout the entire processor
Data Source
AI summary
A Single Event Upset Protector (SEUP) solution receives assembly code corresponding to a program and generates a primary thread and a shadow thread, each operating in different address spaces of an unhardened processor. The SEUP solution inserts swizzling operations in the shadow thread to maintain canonical pointer values and inserts turnouts in both threads to look for checkpoints. A SEUP solution insert a SEUP (e.g., hardware) between the unhardened processor and (a) a data memory and (b) a peripheral bus. The SEUP caches memory writes to the data memory and I/O writes to the peripheral bus. The SEUP restarts the primary thread and the shadow thread at a previous checkpoint when a watchdog indicates a hang and when the cached memory writes and the cached I/O writes by the primary thread to not match the cached memory writes and the cached I/O writes by the shadow thread.