SGD Transistor Program-Verify with Reversed Current Flow
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Solution Overview
Problem
In semiconductor memory devices, particularly in 3D NAND structures, the programming and verification of select gate transistors (SGD) are challenging due to non-uniform doping and varying threshold voltages, which affect the conductive and non-conductive states required for proper programming and data retention, leading to issues like slower programming and increased program disturb.
Innovation Solution
The programming of SGD transistors is performed under similar biasing conditions as memory cells, using a program-verify test with a current flowing from the source end to the drain end (Iwell-bl) to ensure optimal conductive or non-conductive states, and the process is optimized by separately testing odd- and even-numbered NAND strings to avoid bit line-to-bit line coupling, allowing for concurrent testing of memory cells with a different current flow direction (Ibl-well).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If select gate transistors are programmed with conventional biasing methods, then programming speed may be improved, but threshold voltage distribution becomes wide and programming reliability deteriorates
Solution Approach 1:
The patent applies parameter changes by switching the biasing configuration from conventional mode to a mode where the bit line is connected to the source and the well is connected to the drain. This parameter change in voltage application method enables accurate threshold voltage control during programming, achieving both fast programming speed and narrow threshold voltage distribution for high reliability
2Reliability
If select gate transistors are programmed accurately with narrow threshold voltage distribution, then programming reliability is improved, but programming speed decreases
Solution Approach 1:
The patent resolves this contradiction through parameter changes in the biasing configuration. By connecting the bit line to source and well to drain during programming, the method achieves both accurate threshold voltage control (narrow distribution) and maintains high programming speed, eliminating the traditional trade-off between reliability and speed
3Productivity
If program-verify testing is performed on all NAND strings simultaneously, then productivity is improved, but bit line coupling interference increases and measurement precision deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the program-verify testing into separate groups based on bit line coupling relationships. Odd-numbered and even-numbered NAND strings are tested in different sequences, preventing simultaneous activation of coupled bit lines. This segmentation maintains high productivity while eliminating measurement interference for precise verification
4Ease of operation
If conventional program-verify testing is used for select gate transistors, then ease of operation is maintained, but power consumption increases due to unnecessary current flow
Solution Approach 1:
The patent applies parameter changes by reversing the conventional current flow direction for select gate transistor testing. By connecting bit line to source and well to drain (opposite of memory cell testing), the method achieves accurate SGD verification while minimizing unnecessary current flow, reducing power consumption without complicating the operation
Data Source
AI summary
A memory device and associated techniques for programming a select gate transistor. The programming of the select gate transistors in a NAND string is performed under similar biasing as is seen during the programming of a memory cell, when the select gate transistors are required to be in the conductive or non-conductive state for selected and unselected NAND strings, respectively. Program-verify tests for the select gate transistors use a current which flows from the source end to the drain end of the NAND string, and can be performed separately for odd- and even-numbered NAND strings, to avoid the effects of bit line-to-bit line coupling. The tests account for uneven doping in the channel of the select gate transistor. Program-verify tests for the memory cells use a current which flows from the drain end to the source end and can be performed concurrently.