SGLNVM Cell Size Reduction via Self-Aligned Etch
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Solution Overview
Problem
Conventional EEPROM fabrication processes for CMOS logic technology nodes are complex and costly due to additional process steps required for extra charge storage layers, leading to increased fabrication costs and longer process times, and face issues with programming/read disturbances and poor endurance cycling.
Innovation Solution
The implementation of Scalable Gate Logic Non-Volatile Memory (SGLNVM) arrays with a self-aligned etch process to eliminate the gate end-cap, reducing the unit cell size to 12 F2, where F is the minimal feature size, and omitting the storage stacks, thereby simplifying the process and reducing costs while maintaining device yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EEPROM fabrication process with extra charge storage layers is used, then charge storage capability is improved, but fabrication cost and process complexity increase
Solution Approach 1:
The patent extracts and removes the extra charge storage layers (floating gate or ONO stack) from the conventional EEPROM structure, retaining only the control gate layer. This simplifies the fabrication process to be compatible with standard CMOS logic processes while maintaining non-volatile memory functionality through the scaled-down transistor geometry and paired-cell configuration.
Solution Approach 2:
The control gate in the simplified structure serves multiple functions: it acts as both the control electrode for the MOSFET and the charge storage element for the non-volatile memory. This multi-functionality eliminates the need for separate floating gate structures while maintaining EEPROM capabilities.
2Reliability
If conventional EEPROM fabrication process with extra charge storage layers is used, then charge storage capability is improved, but process time increases
Solution Approach 1:
By removing the floating gate and ONO stack deposition steps, the patent significantly reduces the number of fabrication process steps. The simplified process uses only the standard CMOS control gate formation, eliminating multiple film deposition, etching, and photolithography steps that would otherwise be required.
3Reliability
If gate end-cap is included in SGLNVM arrays, then device yield is improved, but unit cell area increases
Solution Approach 1:
The patent employs a self-aligned etch process where the etch pattern automatically defines both the memory cell boundaries and the gate structure. This self-alignment eliminates the need for separate gate end-cap extensions that would otherwise be required to compensate for alignment variations, reducing cell area while maintaining yield through process self-correction.
4Ease of operation
If conventional NOR flash array architecture is used, then programming capability is improved, but area efficiency deteriorates
Solution Approach 1:
The patent transitions from the conventional planar NOR flash layout to a scaled-down configuration where the paired-cell structure and self-aligned etch enable denser packing. By changing the dimensional arrangement and eliminating gate end-caps, the patent achieves 50% area reduction while maintaining the essential programming functionality through the simplified control gate structure.
Data Source
AI summary
Scalable Logic Gate Non-Volatile Memory (LGNVM) NOR-type arrays fabricated by the standard CMOS logic technologies have been applied for the embedded flash solutions in digital circuitries. To significantly reduce the memory array sizes from the previous fabrications, we have applied the topological regularity of memory cells in the arrays and a self-aligned etch process step to eliminate the gate end-caps in the memory areas. Without scarifying the memory array yields, the minimal unit cell size of 12 F2 for the LGNVM NOR flash arrays can be achieved by this method, where F is the minimal feature size for a specific CMOS logic process technology node.