SGLNVM Interconnection Matrix for Reconfigurable IC Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IC chip interconnection methods lack flexibility and cost-effectiveness for configuring circuit routings, as One-Time-Programmable (OTP) fuses are irreversible and costly for applications requiring multiple reconfigurations, while existing non-volatile memory solutions do not provide sufficient programmable wiring capacity.
Innovation Solution
A Scalable Gate Logic Non-Volatile Memory (SGLNVM) array in NOR configuration, using N-type or P-type non-volatile memory cells with threshold voltage programming, allows for reversible configuration of interconnection matrices through Fowler-Nordheim or Band-to-Band tunneling, enabling multiple programming cycles and flexible wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If OTP fuses are used for interconnection configuration, then the wiring configuration is fixed after fabrication, but the flexibility of changing wiring configuration is lost and development cost increases
Solution Approach 1:
The patent applies MTP non-volatile memory devices that allow the interconnection matrix to be reconfigured multiple times after fabrication. The memory devices can be programmed and erased repeatedly, enabling dynamic changes to wiring configurations without requiring mask revision or silicon re-fabrication, thus resolving the contradiction between configuration stability and reconfiguration flexibility
Solution Approach 2:
The patent utilizes the threshold voltage parameter of MTP non-volatile memory devices to encode connection states. By changing the threshold voltage parameter through programming and erasing operations, the interconnection configuration can be dynamically adjusted multiple times, maintaining both reliability and adaptability
2Adaptability or versatility
If large amounts of OTP fuses are used for multiple times configurable wiring capacity, then the wiring reconfiguration capability is achieved, but the cost becomes unrealistic
Solution Approach 1:
The patent employs MTP non-volatile memory devices that serve multiple functions: they act as both storage elements and interconnection switches. These devices can be programmed to different states multiple times, providing universal reconfiguration capability for various wiring patterns without requiring separate fuse structures, thereby reducing manufacturing cost while maintaining high adaptability
Solution Approach 2:
The patent uses MTP memory devices that can replicate connection patterns through programming. The same physical memory device can be programmed to represent different connection states across multiple configurations, effectively copying the interconnection pattern as needed without requiring additional physical fuse elements for each configuration
3Productivity
If semiconductor non-volatile memory is applied for interconnection matrix, then the programming-erase cycling capability is achieved, but the threshold voltage stability during operation must be maintained
Solution Approach 1:
The patent designs the non-volatile memory devices with sufficient threshold voltage margin between programmed and unprogrammed states. This beforehand cushioning ensures that even after multiple programming-erase cycles, the threshold voltage remains stable enough to distinguish connection states, preventing read disturbance and maintaining reliability throughout the device lifecycle
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SGLNVM array provides a cost-effective and flexible means for configuring and reconfiguring IC chip interconnections, offering better delay speeds and reduced development costs by enabling multiple programming cycles without the need for extensive re-masking and re-fabrication.
Implementation Method 1
reversible configuration of interconnection matrices through Fowler-Nordheim or Band-to-Band tunneling
Implementation Method 2
reversible configuration of interconnection matrices through Fowler-Nordheim or Band-to-Band tunneling
Implementation Method 3
Semiconductor non-volatile memory is a type of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) capable of storing charges to alter the threshold voltages of the MOSFET
Data Source
AI summary
An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC).