Self-Aligned SGT Gate Electrode Fabrication
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Solution Overview
Problem
Conventional methods for producing surrounding gate transistors (SGTs) face challenges in reducing parasitic capacitance between the gate line and substrate, require thick gate material deposition, and are not self-aligned, leading to void formation and difficulties in working with gate material.
Innovation Solution
A self-aligned process is developed using a method that forms a fin-shaped silicon layer, a pillar-shaped silicon layer, and a gate insulating film, followed by deposition of a metal film and polysilicon film, with anisotropic etching to create a gate line, and subsequent removal of exposed polysilicon and metal films to form a metal gate electrode, reducing parasitic capacitance and using a thin gate material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick gate material is deposited between silicon pillars with narrow intervals, then the gate material can sufficiently cover the space, but voids are formed between the silicon pillars leading to holes in the gate material after etch back
Solution Approach 1:
A gate oxide film is formed on the silicon pillars before depositing the gate material. This preliminary oxidation creates a protective layer that prevents void formation during subsequent material deposition and processing steps, ensuring continuous gate material coverage without holes.
Solution Approach 2:
A thin polysilicon layer is deposited as an intermediary between the gate oxide film and the final gate material. This intermediate layer fills potential voids and provides a continuous base that prevents hole formation in the final gate structure after etch back processing.
2Manufacturing precision
If a resist covering the upper portion of the silicon pillar is formed to create a gate line, then the gate line can be defined, but the process is not self-aligned and requires additional steps
Solution Approach 1:
The gate line formation is merged with the gate electrode formation process. The same etching process that defines the gate electrode also defines the gate line, eliminating the need for separate resist patterning steps and achieving self-alignment between gate electrode and gate line positions.
Solution Approach 2:
The gate electrode structure itself serves as the alignment reference for gate line formation. The etching process automatically aligns the gate line with the gate electrode without requiring external resist patterns, making the process self-aligned and reducing step count.
3Object-affected harmful factors
If a first insulating film is formed around the fin-shaped silicon layer and etched back to decrease parasitic capacitance, then the capacitance between gate line and substrate is reduced, but additional steps are required
Solution Approach 1:
The insulating film formation around the fin-shaped silicon layer is merged with the gate oxide film formation process. The same oxidation process that creates the gate oxide also forms the insulating film around the fin, eliminating separate deposition and etch back steps while achieving parasitic capacitance reduction.
Solution Approach 2:
The gate oxide film formation process serves multiple functions: it creates the gate insulator, forms the insulating film around the fin-shaped silicon layer for capacitance reduction, and provides the base for subsequent gate material deposition. This multi-functionality reduces overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, allows for a self-aligned process, and increases integration density by using a laminated gate structure with direct contact between silicide and metal film, decreasing resistance.
Implementation Method 1
a metal film 108 and a polysilicon film 109 thinner than the width of the pillar-shaped silicon layer 106 are formed around the gate insulating film 107
Implementation Method 2
a gate line 111b is formed by performing anisotropic etching
Data Source
AI summary
A SGT-production method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer, where the pillar-shaped silicon layer has the same width as the fin-shaped silicon layer, forming a gate insulating film around the pillar-shaped silicon layer, forming, around the gate insulating film, a metal film and a polysilicon film thinner than the width of the pillar-shaped silicon layer, forming a third resist for forming a gate line, performing anisotropic etching to form the gate line, depositing a fourth resist, exposing the polysilicon film on a sidewall of an upper portion of the pillar-shaped silicon layer, removing the exposed polysilicon film by etching, removing the fourth resist, removing the metal film by etching, and forming a gate electrode connecting to the gate line.