SGT 4F2 Memory Cell Bit Line Resistance Reduction
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Solution Overview
Problem
Conventional SGT-DRAMs face challenges in achieving a 4F2 memory cell size with low bit line resistance while maintaining sufficient production yield, as high-resistance bit lines increase operation speed issues and require complex bit line configurations.
Innovation Solution
A semiconductor storage device with a memory cell array where high-resistance bit lines are backed with low-resistance interconnection lines, using a structure and layout similar to regular memory cells to minimize area increases and ensure stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If bit line is formed using N+ diffusion layer to achieve 4F2 cell size, then memory cell area is reduced, but bit line resistance increases significantly
Solution Approach 1:
The bit line is constructed as a composite structure with two layers: a first bit line layer (N+ diffusion layer) and a second bit line layer (metal film such as tungsten) formed on top of it. This composite structure combines the advantages of both materials to achieve both small cell area and low resistance.
Solution Approach 2:
The invention changes the physical parameters of the bit line by adding a metal film layer with inherently lower resistance than the N+ diffusion layer, thereby reducing the overall resistance while maintaining the diffusion layer for area efficiency.
2Speed
If bit line resistance is reduced by using metal film, then operation speed improves, but memory cell area increases beyond 4F2
Solution Approach 1:
By forming a metal film layer on the N+ diffusion layer, the invention achieves low resistance (fast operation) while maintaining the compact 4F2 cell area through the vertical stacking of materials rather than horizontal expansion.
Solution Approach 2:
The solution transitions from a planar bit line structure to a vertical stacked structure, utilizing the third dimension (depth) to accommodate the metal film layer, thereby reducing resistance without increasing the planar cell area.
3Productivity
If bit line is formed in minimum fabrication size to achieve 4F2 cell size, then integration density increases, but bit line resistance increases causing slower operation
Solution Approach 1:
The composite bit line structure with N+ diffusion layer and metal film layer enables minimum fabrication size for high integration density while the metal film component provides low resistance for fast operation speed.
Solution Approach 2:
The invention applies different material properties to different parts of the bit line: the N+ diffusion layer provides the structural foundation and connectivity, while the metal film layer provides the low-resistance conduction path, optimizing both density and speed locally.
Data Source
AI summary
In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which causes a problem of slowdown in memory operation speed. The present invention provides a semiconductor storage device comprising an SGT-based 4F2 memory cell, wherein a bit line-backing cell having the same structure as that of a memory cell is inserted into a memory cell array to allow a first bit line composed of a diffusion layer to be backed with a low-resistance second bit line through the bit line backing cell, so as to provide a substantially low-resistance bit line, while suppressing an increase in area of the memory cell array.