SGT Memory Cell Matrix Layout for Capacitive Coupling Control
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory cells face issues with erroneous reading and rewriting due to large capacitive coupling between the word line and floating body, leading to insufficient potential difference margins during writing and reading operations.
Innovation Solution
A semiconductor element memory device with a matrix of memory cells, each formed of one or two semiconductor elements, featuring a vertical semiconductor base with impurity regions and gate conductor layers, and controlled voltage applications to manage data retention and discharge, utilizing a larger gate capacitance for reduced capacitive coupling and improved data stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a capacitorless single-transistor DRAM memory cell is used, then device integration density is improved, but capacitive coupling noise increases causing erroneous reading and rewriting
Solution Approach 1:
The gate conductor layer is divided into two separate layers: a first gate conductor layer and a second gate conductor layer. This segmentation allows independent control of capacitive coupling to the channel region and floating body, respectively, enabling suppression of noise while maintaining integration density benefits
Solution Approach 2:
A gate insulating layer is introduced between the semiconductor base and the gate conductor layers. This intermediary layer reduces direct capacitive coupling between the word line and the floating body, thereby suppressing noise that causes erroneous reading and rewriting while preserving the capacitorless structure
2Speed
If large capacitive coupling exists between word line and floating body, then write operation speed is improved, but potential difference margin becomes insufficient leading to reading errors
Solution Approach 1:
The gate conductor layer is segmented into two distinct layers with different functions: the first gate conductor layer maintains strong coupling for fast writing, while the second gate conductor layer provides controlled coupling for stable reading, thus resolving the speed-reliability trade-off
Solution Approach 2:
Different regions of the gate structure are assigned different coupling characteristics: the first gate conductor layer is optimized for strong local coupling to enable fast writing, while the second gate conductor layer provides moderated local coupling to ensure sufficient potential difference margin for reliable reading
3Stability of the object's composition
If voltage control is applied to manage data retention, then data stability is improved, but device complexity increases
Solution Approach 1:
The dual gate conductor layer structure serves multiple functions simultaneously: it controls capacitive coupling for noise suppression, enables differential voltage control for data retention, and maintains the capacitorless single-transistor configuration. This multi-functionality achieves data stability without proportionally increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitive coupling noise, ensuring accurate data retention and reading by controlling voltages to maintain stable potential differences, enabling reliable data storage and retrieval.
Implementation Method 1
a memory write operation of controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region to hold, inside the semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current
Implementation Method 2
a memory write operation of controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region to hold, inside the semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current
Data Source
AI summary
A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.