Surrounding Gate Transistor NOR Decoder Layout
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Solution Overview
Problem
The increasing integration of transistors in semiconductor chips leads to space constraints and the need for compact designs, as traditional planar transistors require isolation and body terminals, which occupy additional area.
Innovation Solution
The use of surrounding gate transistors (SGTs) with a silicon pillar structure eliminates the need for well isolation and body terminals, allowing for a compact layout by arranging transistors in a layered manner perpendicular to the substrate, with gates surrounding the pillars and source and drain regions on opposite sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar transistors are used with complete isolation of n-well and p-well regions, then transistor functionality is ensured, but the area occupied by isolation structures and body terminals increases
Solution Approach 1:
The patent transitions from planar transistors to vertically stacked transistors where the source, gate, and drain are arranged in a direction perpendicular to the substrate. The gate surrounds an island-shaped semiconductor layer, creating a three-dimensional structure that eliminates the need for lateral isolation structures and body terminals, thereby reducing device area while maintaining functionality
Solution Approach 2:
The surrounding gate structure serves multiple functions simultaneously: it provides electrical control of the channel, acts as the gate electrode, and eliminates the need for separate isolation structures and body terminals. This multi-functional design reduces the number of components needed and simplifies the overall device structure
2Area of stationary object
If surrounding gate transistors are used to reduce area, then device compactness is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming the island-shaped semiconductor layer, depositing the gate insulating film, forming the surrounding gate electrode, and creating source and drain regions. This segmentation of the manufacturing process makes the complex three-dimensional structure achievable through standard semiconductor fabrication techniques
Solution Approach 2:
The gate electrode is formed by depositing conductive material that completely surrounds the island-shaped semiconductor layer in a vertical stack. This nested configuration where the gate encloses the semiconductor layer is achieved through conformal deposition techniques, simplifying the manufacturing of the three-dimensional structure
Data Source
AI summary
A semiconductor device includes a 2-input NOR decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.