SGT Semiconductor Pillar Formation via Shape-Selective Etching
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Solution Overview
Problem
The challenge is to increase the integration density of semiconductor devices using surrounding gate MOS transistors (SGTs) while maintaining high positional accuracy in forming semiconductor pillars, which is crucial for scaling down circuit chips and improving performance.
Innovation Solution
A method involving multiple material layer formation and etching steps using masks of various shapes to form semiconductor pillars with circular cross-sections, ensuring precise alignment and self-alignment techniques to create SGTs with enhanced current drive capability and reduced protrusion from the circuit region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar-type MOS transistors are used, then manufacturing process is simpler, but integration density is lower
Solution Approach 1:
The patent transitions from planar-type MOS transistors to surrounding gate MOS transistors by changing the channel orientation from in-plane to vertical direction. This dimensional change enables higher integration density as multiple channels can be packed in the same footprint area, achieving the goal of increased productivity without excessive complexity increase
2Area of stationary object
If SGTs are used to increase density, then circuit chip area is reduced, but positional accuracy in forming semiconductor pillars becomes more critical and difficult to maintain
Solution Approach 1:
The patent forms the semiconductor pillar before forming the gate insulating layer and gate electrode. This preliminary action establishes the pillar position and dimensions first, allowing subsequent layers to be formed with reference to this established structure, thereby maintaining manufacturing precision while achieving high density
Solution Approach 2:
The semiconductor pillar structure serves as a self-aligning reference for subsequent processing steps. The pillar's own geometry and position automatically define the placement of gate insulating layers and electrodes, reducing the need for additional alignment operations and maintaining precision in the reduced chip area
3Manufacturing precision
If multiple material layers and etching steps are used to form circular semiconductor pillars, then positional accuracy is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the pillar formation process into distinct stages: forming a first semiconductor layer with a first shape, then forming a second semiconductor layer with a second shape. This segmentation allows each layer to be optimized independently, achieving high positional and shape accuracy through controlled etching of each segment rather than attempting to form the final complex structure in a single step
Data Source
AI summary
Isotropic etching is conducted by using SiN layers that are disposed on i-layers having an island structure on an i-layer substrate and have the same rectangular shape in a plan view as the i-layers. As a result, SiO2 layers each having a circular shape in a plan view are formed. Then the SiN layers are removed and the i-layers are etched by using the SiO2 layers as a mask to form Si pillars. Then surrounding gate MOS transistors are formed in the Si pillars.