Shallow Trench Isolation Etch Control for Uniform STI Thickness
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Solution Overview
Problem
The formation of shallow trench isolations (STIs) in semiconductor devices, particularly in gate-all-around (GAA) transistors, results in a dishing effect due to differing etch rates of liner and insulating layers, leading to uneven thickness and potential damage to channel regions during ion implantation processes.
Innovation Solution
An ion implantation process is employed to introduce impurities into the insulating layer, altering the Si—O bonding and increasing the etch resistance, thereby reducing the etch rate difference between the liner and insulating layers, mitigating the dishing effect and ensuring consistent STI thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional STI formation is used without ion implantation, then the process is simpler and faster, but the etch rate difference between liner and insulating layers causes dishing effect and uneven thickness
Solution Approach 1:
Ion implantation is performed on the insulating layer before the etch process to pre-modify its etch resistance properties. This preliminary action ensures that during subsequent etching, the insulating layer etches at a rate closer to the liner layer, reducing dishing effect and improving thickness uniformity without requiring complex real-time control during etching
Solution Approach 2:
The etch resistance parameter of the insulating layer is changed through ion implantation, which introduces impurities that alter the Si-O bonding characteristics. This parameter change reduces the etch rate difference between the insulating layer and liner layer, thereby mitigating the dishing effect and achieving more uniform STI thickness
2Manufacturing precision
If high etch resistance insulating layer is used, then dishing effect is reduced, but channel regions may be damaged during ion implantation
Solution Approach 1:
Ion implantation is selectively applied only to the insulating layer regions that will become STI regions, not to the channel regions. This local quality approach modifies the etch resistance of the insulating layer where needed while leaving the channel regions unaffected, thus achieving both dishing reduction and channel protection
Solution Approach 2:
The insulating layer serves as an intermediary that receives the ion implantation treatment and translates it into etch resistance modification. This intermediary role protects the channel regions from direct ion exposure while still achieving the desired etch rate adjustment in the STI regions through the modified insulating layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ion implantation process enhances the etch resistance of the insulating layer, reducing the dishing effect and maintaining consistent STI thickness, thus protecting the channel regions and improving the integrity of GAA transistors.
Implementation Method 1
An ion implantation process is employed to introduce impurities into the insulating layer, altering the Si—O bonding and increasing the etch resistance
Data Source
AI summary
A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.