Electronic apparatus and clock generating method thereof

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Solution Overview

Problem

Modern electronic devices supporting multiple communications standards face challenges in accurately generating baseband clocks due to frequency offsets, requiring multiple precise oscillators which are costly and inefficient to integrate.

Innovation Solution

An electronic apparatus utilizing a single reference oscillator, coupled with auto frequency control units and frequency synthesizers, adjusts baseband clocks across different communications modules to compensate for frequency offsets, enabling the generation of baseband clocks for various standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple precise oscillators are used for different communications modules, then demodulation quality is improved, but manufacturing cost increases

Engineering Contradiction:
Improvedemodulation qualityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges multiple oscillator functions into a single reference oscillator that serves all communications modules. The frequency synthesizers generate different baseband clocks from this single reference source, eliminating the need for multiple separate oscillators while maintaining demodulation quality through frequency offset compensation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces frequency synthesizers as intermediary devices between the single reference oscillator and the communications modules. These synthesizers convert the reference clock into module-specific baseband clocks with appropriate frequency offsets, acting as mediators that enable one oscillator to serve multiple purposes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If a single precise oscillator is shared across multiple communications modules, then manufacturing cost is reduced, but frequency offset compensation becomes more complex

Engineering Contradiction:
Improvemanufacturing costVSAvoidfrequency offset compensation complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent changes the frequency parameter of the baseband clock dynamically through frequency synthesizers. By adjusting the frequency offset parameter based on detected conditions, the system compensates for frequency mismatches between modules and base stations without requiring multiple oscillators.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback mechanisms where frequency offsets are detected and used to adjust the baseband clock frequency. The detected frequency offset feeds back to the frequency synthesizer, which then adjusts the baseband clock to compensate for the mismatch, creating a closed-loop control system.

Inventive Principle:
Principle #23Feedback

3Reliability

If baseband clock frequency is adjusted dynamically, then frequency offset is compensated, but clock generation stability may be affected

Engineering Contradiction:
Improvefrequency offset compensationVSAvoidclock generation stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The system performs self-adjustment by detecting its own frequency offset and automatically compensating through the frequency synthesizer. The communications module monitors its own performance and adjusts its baseband clock without external intervention, maintaining both compensation accuracy and stability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8531216B1Electronic apparatus and clock generating method thereof
Publication Date: 2013.09.10 MEDIATEK INC
  • US8531216B1 patent drawing
  • US8531216B1 patent drawing
  • US8531216B1 patent drawing

AI summary

The present invention discloses an electronic apparatus. The electronic apparatus comprises a reference oscillator, for generating a reference clock; a first communications module, comprising a first auto frequency control unit, for detecting a first frequency offset between the first communications module and a first communication device and generating a first detecting result; and a first frequency synthesizer, for adjusting the reference clock according to the first detecting result, to generate a first baseband clock; and a second communications module, comprising a second auto frequency control unit, for detecting a second frequency offset between the second communications module and a second communication device and generating a second detecting result; a second frequency synthesizer, for receiving and outputting the first baseband clock; and a compensation unit, for adjusting the first baseband clock according to the first detecting result and the second detecting result, to generate a second baseband clock.