Shared Bit Line Architecture for NAND Flash Memory Density
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Solution Overview
Problem
Conventional NAND Flash memory devices face challenges in shrinking array pitch below 50 nm and improving performance, with high bit line capacitance and contact resistance issues, leading to reliability problems and increased power consumption.
Innovation Solution
A shared bit line approach and local switching structure are implemented, using a regular array of select gate stripes self-aligned to active areas, with checkerboard-type contacts and alternating select gate stripes, to reduce bit line capacitance and contact resistance, and enhance manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If array pitch is shrunk below 50 nm to increase memory density, then storage capacity is improved, but bit line capacitance and contact resistance increase leading to reliability problems
Solution Approach 1:
The bit line structure is segmented into multiple shared bit lines that serve different memory cell string groups. This segmentation reduces the total capacitance burden on each individual bit line, allowing pitch shrinkage while maintaining signal integrity and reliability.
Solution Approach 2:
The patent introduces a three-dimensional contact structure with multiple contact levels and intermediate contact layers. This vertical dimensionality change reduces contact resistance by providing multiple parallel conduction paths without increasing lateral pitch.
2Quantity of substance
If array pitch is reduced to improve memory density, then storage capacity increases, but power consumption increases due to higher capacitance
Solution Approach 1:
Memory cell strings are divided into multiple groups, each served by dedicated shared bit lines. This segmentation reduces the total capacitance that must be charged/discharged during operations, directly reducing power consumption while maintaining high density through efficient spatial arrangement.
Solution Approach 2:
Shared bit lines serve multiple memory cell string groups simultaneously, reducing the total number of bit lines required. This multi-functionality reduces overall capacitance and power consumption while achieving high memory density through resource sharing.
3Ease of manufacture
If conventional contact structure is used with shrunk pitch, then manufacturing is simpler, but contact resistance increases leading to performance degradation
Solution Approach 1:
The contact structure transitions from a two-dimensional planar contact to a three-dimensional multi-level contact architecture. Intermediate contact layers and vertical contact holes provide additional conduction paths that reduce contact resistance without complicating the manufacturing process beyond standard multi-layer deposition techniques.
Solution Approach 2:
Intermediate contact layers are introduced between the bit line and memory cell string contacts. These intermediary layers serve as transition zones that reduce contact resistance by providing better material interfaces and multiple conduction paths, while still using conventional fabrication processes.
4Use of energy by moving object
If shared bit line approach is implemented to reduce capacitance, then power consumption decreases, but device complexity increases
Solution Approach 1:
Multiple memory cell string groups are merged onto shared bit lines, consolidating the bit line structure. This merging reduces the total number of bit lines and associated capacitance, lowering power consumption while the modular grouping strategy keeps the structure manageable and not overly complex.
Solution Approach 2:
The shared bit line structure is implemented with local variations in grouping and allocation optimized for specific regions. This local quality approach allows the structure to be adapted to different areas of the memory device, managing complexity through regional optimization rather than uniform design.
Data Source
AI summary
Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.