Shared Bit Line String Architecture for Memory Cell Selection
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Solution Overview
Problem
The challenge in semiconductor memory technology is the difficulty in fabricating closely spaced transistors with different threshold voltages in shared bit line string architectures, particularly due to issues with ion implantation and the fabrication of select transistors using thin charge storage layers, which complicates programming and reading of memory cells without additional processing steps.
Innovation Solution
The implementation of a shared bit line string architecture that pairs memory cells and select devices using the same transistor structure, allowing for programming and reading without the need for additional processing steps by utilizing conductive or non-conductive charge storage layers, and controlling selection transistors to manage shared bit lines effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional separate bit line architectures are used, then each memory cell can be independently accessed, but bit line resistance and capacitance increase, reducing programming and reading efficiency
Solution Approach 1:
The patent merges two bit lines into a single shared bit line that serves multiple memory cells. Specifically, a first bit line and a second bit line are combined into a shared bit line that is connected to multiple NAND strings, reducing the total number of bit lines and thereby reducing bit line resistance and capacitance while improving programming and reading efficiency
2Manufacturing precision
If closely spaced transistors with different threshold voltages are fabricated using traditional ion implantation, then select transistors can be differentiated, but the fabrication process becomes significantly more complex
Solution Approach 1:
The patent applies local quality by giving different threshold voltages to specific transistors through selective doping during the formation process. First and second select transistors are formed with first and second threshold voltages respectively, allowing differentiation of select transistors connected to the shared bit line while using a unified fabrication process that doesn't require complex post-fabrication ion implantation steps
Solution Approach 2:
The patent changes the threshold voltage parameter of select transistors during the formation process itself, rather than modifying them afterward. By controlling the doping concentration and type during transistor formation, the patent establishes different threshold voltages for different select transistors, simplifying the overall fabrication process
3Area of stationary object
If thin charge storage layers are used in memory cells, then device area is reduced, but additional processing steps are required for programming and reading operations
Solution Approach 1:
The patent performs preliminary action by pre-configuring the shared bit line and select transistors with appropriate threshold voltages and connections before memory operations. The shared bit line is预先 connected to multiple NAND strings with properly configured select transistors, allowing standard programming and reading operations to proceed without additional complex processing steps even though thin charge storage layers are used
Data Source
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Figure 4A
AI summary
Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.