Shared-Bus Data Transfer for Low-Latency HWA Processing
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Solution Overview
Problem
Existing data processing systems using Service Function Chaining (SFC) suffer from increased processing delays due to unnecessary CPU involvement in tasks that can be handled by Hardware Accelerators (HWAs), leading to inefficient data reconstruction and transfer control, which accumulates delays in cloud services requiring low latency.
Innovation Solution
A data transfer device and data processing device that perform packet routing and arbitration, utilizing a shared bus for efficient communication between HWAs, reducing CPU involvement and optimizing data transfer through packet analysis, reconstruction, and order control, while managing communication at the network level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPU is used to control HWA and perform data reconstruction and transfer control, then data processing can be performed, but processing delay increases
Solution Approach 1:
The patent extracts the CPU from the data transfer control path by introducing a dedicated transfer device that operates independently. The transfer device handles packet routing, arbitration, and HWA coordination directly, removing these tasks from the CPU's responsibility and eliminating the associated processing delays while maintaining full data processing capability.
Solution Approach 2:
The transfer device acts as an intermediary between the HWA and the network interface card (NIC). It manages data transfer control and arbitration without CPU involvement, serving as a dedicated mediator that reduces processing delay while ensuring reliable data processing through structured transfer control mechanisms.
2Productivity
If CPU performs data reconstruction and transfer control in host application, then data can be processed by HWA, but system delay accumulates due to software processing
Solution Approach 1:
The patent replaces the software-based CPU control mechanism with a hardware-based transfer device. This substitution eliminates the overhead of software processing, driver communication, and kernel mode transitions, achieving high productivity through hardware-accelerated transfer control while minimizing system delay.
Solution Approach 2:
The transfer device performs data reconstruction and transfer control autonomously without CPU intervention. It self-manages packet routing decisions, arbitration with other HWAs, and data flow control, enabling high throughput while reducing system delay by eliminating the need for CPU-mediated software processing.
3Adaptability or versatility
If multiple communication paths are used between NIC and HWA, then data transfer flexibility increases, but unnecessary communication delays occur
Solution Approach 1:
The patent merges the transfer control functionality directly into the transfer device that is already present in the HWA. This consolidation eliminates unnecessary communication hops between NIC, driver, kernel, and HWA by providing a unified transfer control mechanism that operates locally at the HWA level, maintaining flexibility while reducing communication delay.
Data Source
AI summary
A data transfer device transfers a received packet. If the transfer destination of the received packet is a data processing device under control, the data transfer device (confirms the state of a shared bus, and if the shared bus is usable, transfers the packet to the data processing device of the transfer destination via the shared bus, gives the use right of the shared bus to one of the data processing devices in response to communication requirements from the data processing devices, and receives, via the shared bus, a packet from the data processing device given the use right.