Shared CDR Circuit for Multi-Pad Memory Clock Recovery
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Solution Overview
Problem
Conventional semiconductor memory devices require large area and high power consumption due to the numerous CDR circuits needed for high-speed signal and data transmission, limiting the number of data transmission channels.
Innovation Solution
Grouping signal input/output pads to share a clock data recovery (CDR) circuit, with phase detection units and notification units to detect and adjust signal phases, converting parallel signals to serial signals for efficient data processing and transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each data pad has a dedicated CDR circuit for high-speed signal recovery, then signal transmission reliability is improved, but the area occupied by CDR circuits increases and power consumption rises
Solution Approach 1:
Multiple CDR circuits are merged into a single shared CDR circuit that serves multiple data pads. The phase detection units and delay units are共用 among different data pads, allowing the system to maintain high-speed signal recovery capability while significantly reducing the total area occupied by CDR circuits and lowering power consumption.
Solution Approach 2:
The shared CDR circuit is designed to handle multiple data pads universally. The phase detection units can detect phases from different data pads, and the delay units can adjust delays for multiple channels, making the CDR circuit multi-functional and applicable to various data transmission channels without requiring dedicated circuits for each pad.
2Measurement precision
If each data pad has a dedicated CDR circuit, then clock data recovery accuracy is improved, but the number of data transmission channels is limited
Solution Approach 1:
Multiple CDR circuits are merged into a single shared CDR circuit that serves multiple data pads. The phase detection units and delay units are共用 among different data pads, allowing the system to maintain high-speed signal recovery capability while significantly reducing the total area occupied by CDR circuits and lowering power consumption.
Solution Approach 2:
The shared CDR circuit incorporates dynamic control mechanisms where the phase detection units can sequentially or simultaneously detect phases from multiple data pads, and the delay units can dynamically adjust delays for different channels based on detected phase differences. This dynamic operation enables the circuit to adapt to multiple data transmission channels while maintaining recovery accuracy.
3Measurement precision
If multiple CDR circuits are used for each data pad, then signal phase detection accuracy is improved, but power consumption increases
Solution Approach 1:
Multiple CDR circuits are merged into a single shared CDR circuit that serves multiple data pads. The phase detection units and delay units are共用 among different data pads, allowing the system to maintain high-speed signal recovery capability while significantly reducing the total area occupied by CDR circuits and lowering power consumption.
Data Source
AI summary
Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.