Shared Debug Controller for Multi-Core ICs
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Solution Overview
Problem
Multi-core integrated circuits often have only a single debug port, making it difficult to individually test or debug multiple logic cores using existing JTAG or similar interfaces, as these interfaces are not designed to handle multiple cores simultaneously.
Innovation Solution
A multi-core integrated circuit is configured with a shared debug controller and core-specific debug controllers to manage a single shared debug port, allowing individual logic cores to be placed into debug mode and enabling commands to be executed on multiple cores through a mask register, enabling simultaneous debugging of multiple logic cores using existing protocols without modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single shared debug port is used in multi-core integrated circuits, then device complexity is reduced, but the ability to individually test or debug logic cores is limited
Solution Approach 1:
The debug controller is segmented into a shared debug controller and multiple core-specific debug controllers. Each core-specific debug controller is dedicated to a particular logic core, enabling individual core debugging while sharing the common debug port interface. This segmentation allows the single debug port to selectively connect to different cores as needed.
Solution Approach 2:
The shared debug controller serves multiple functions by managing communication between the single debug port and multiple logic cores. It can selectively activate different core-specific debug controllers based on which core needs debugging, making the debug port universal for all cores rather than requiring dedicated ports for each core.
2Power
If multiple logic cores are included in a single integrated circuit, then processing capability is improved, but debugging capability using traditional interfaces is reduced
Solution Approach 1:
The shared debug controller acts as an intermediary between the traditional debug port interface and the multiple logic cores. It translates standard JTAG commands into core-specific debugging operations, allowing existing debugging equipment to work with multi-core systems without modification while maintaining compatibility with traditional debugging protocols.
Solution Approach 2:
The debug system dynamically activates only the necessary core-specific debug controllers based on which core requires debugging. This dynamic selection allows the system to adapt to different debugging scenarios, maintaining versatility across multiple cores while using a fixed single debug port interface.
Data Source
AI summary
A single test access port, such as a JTAG-based debug port may be utilized to perform debug operations on logic cores of a multi-core integrated circuit, such as a multi-core processor. The shared debug port may respond to a particular command to enter a debugging mode and may be configured to forward all commands and data to a debugging controller of the integrated circuit during debugging. A mask register may be used to indicate which logic cores of the multi-core integrated circuit should be debugged. Additionally, custom debugging commands may include mask or core select fields to indicate which logic cores should be affected by the particular command. Debugging mode may be initialized for one or more logic cores either externally, such as be asserted a DBREQ signal, or internally, such as by configuring one or more breakpoints.