Shared Integer Floating Point Divider Logic Unit
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Solution Overview
Problem
Conventional integer division hardware faces a tradeoff between die area usage and latency, and the separation of floating point capability from integer division hardware increases die area, making it difficult to achieve both low die area and low latency.
Innovation Solution
A shared hardware logic unit is used to perform both floating point division and integer division operations, sharing resources such as sparse RAM and on-the-fly state machines, allowing for consistent radix operations and efficient handling of normalization and exceptions, thereby reducing die area and improving latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate floating point hardware is used in addition to integer division hardware, then floating point capability is achieved, but die area increases
Solution Approach 1:
The patent implements a unified division hardware unit that can perform both integer division and floating point division operations. The same hardware resources including the divisor buffer, dividend buffer, quotient buffer, and division logic are shared between integer and floating point operations through a control mechanism that routes operations appropriately, eliminating the need for separate floating point division hardware and reducing die area.
2Area of stationary object
If conventional integer division hardware is designed for low die area, then area usage is reduced, but latency increases
Solution Approach 1:
The patent employs dynamic resource allocation and operational modes within the division hardware. The controller can switch between different operational configurations and optimize the use of hardware resources based on the specific operation type, enabling the hardware to achieve low latency performance while maintaining compact area through efficient dynamic resource management rather than static over-provisioning.
Data Source
AI summary
Embodiments of the inventive concept include a shared hardware integer/floating point divider and square root logic unit, which combines floating point division, floating point square root operations, and/or integer division into one shared hardware design. The shared hardware logic unit can share, for example, a sparse random access memory (sparse RAM) in place of a full partial remainder divisor (PD) table, one or more on-the-fly (OTF) state machines, and/or a data path for integer division, floating point division, and square root operations. The normalization of subnormal numbers and the normalization of signed and unsigned integers can be handled with shared hardware. The division operations and the square root operations can be of the same radix. Early out exceptions and special cases can be automatically handled. Both improved latency and less die area can be achieved in accordance with embodiments of the inventive concept.