Shared DLL Timing Calibration for DDR DRAM Controllers
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Solution Overview
Problem
High-speed operation of DDR DRAM systems poses challenges in accurately determining timing delays for signal synchronization, leading to inefficiencies and increased costs due to the physical size and power consumption of delay locked loop (DLL) circuits, which are necessary for proper data transfer but are expensive and inefficiently laid out.
Innovation Solution
A shared DLL is used in the DRAM controller to support both read and write paths, dynamically updating delay values based on operational mode, and a calibration algorithm trains timing delays to optimize signal synchronization, reducing the number of required DLLs and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate DLL circuits are used for read and write paths in high-speed DDR DRAM controllers, then timing synchronization accuracy is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent combines separate read-DLL and write-DLL circuits into a single shared DLL circuit. The shared DLL receives a single clock signal and generates delayed clock signals for both read and write operations, eliminating the need for duplicate DLL circuits while maintaining timing synchronization accuracy through dynamic delay adjustment for different operational modes.
Solution Approach 2:
The shared DLL circuit is designed to serve multiple functions by dynamically configuring its delay characteristics based on operational mode (read or write). The circuit can adjust its delay parameters to optimize performance for different signal paths, making a single circuit universal for both read and write timing synchronization requirements.
2Adaptability or versatility
If multiple DLL circuits are implemented for read and write operations, then timing delays can be customized for each path, but manufacturing cost and silicon area increase
Solution Approach 1:
The patent merges multiple DLL circuits into one shared circuit, reducing silicon area and manufacturing complexity. The shared DLL maintains adaptability by allowing independent delay programming for read and write operations through configuration registers, enabling customized timing delays without requiring separate physical circuits.
Solution Approach 2:
The shared DLL circuit incorporates dynamic delay adjustment capabilities that allow timing parameters to be customized for different operational modes. The circuit can be programmed with different delay values for read and write paths, providing the versatility of customized timing while using a single static physical structure.
3Device complexity
If dead reckoning is used to determine DLL timing delays during product development, then device complexity is reduced, but timing accuracy deteriorates due to configuration differences
Solution Approach 1:
The patent implements a training sequence mechanism that performs preliminary timing calibration before normal operation. The training sequence sends known test patterns through the memory interface, allowing the system to measure actual timing delays and adjust DLL parameters accordingly, compensating for configuration-specific variations before production use.
Solution Approach 2:
The system incorporates feedback mechanisms where the training sequence results are used to adjust DLL timing parameters. By monitoring the actual signal timing through the memory interface and comparing it against expected values, the system automatically fine-tunes delay settings to achieve accurate timing synchronization for the specific hardware configuration.
Data Source
AI summary
Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).