Shared-Driver Multiplexer for Lower Output Loading
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Solution Overview
Problem
In semiconductor memory systems, existing multiplexers face challenges in minimizing output loading, which limits data transfer bandwidth due to the need for multiple drivers to handle multiple data signals, leading to increased complexity and reduced efficiency.
Innovation Solution
A multiplexer design that utilizes a combination of inverters and transfer gates with NMOS and PMOS transistors to share drivers, allowing for the selection and output of multiple data signals through a single driver, thereby reducing the number of drivers required and minimizing output loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple drivers are used to handle multiple data signals, then data transfer capability is improved, but output loading increases and device complexity increases
Solution Approach 1:
The patent combines multiple driver functions into a single driver by using transfer gates to selectively connect different data signals to the shared driver output. This merging approach maintains the ability to handle multiple data signals while reducing the total number of drivers required, thereby decreasing output loading and device complexity.
Solution Approach 2:
The single driver is designed to perform multiple functions by receiving control signals that enable it to select and output different data signals (first data, second data, third data, or fourth data) based on the state of transfer gates. This multi-functionality allows one driver to replace what would traditionally require multiple dedicated drivers.
2Productivity
If multiple drivers are used to handle multiple data signals, then data transfer capability is improved, but output loading increases
Solution Approach 1:
By merging multiple driver functions into a single driver with selective connectivity through transfer gates, the patent reduces the total output loading on the bus. The single driver shares the output load across multiple time slots or signal selections, thereby maintaining data transfer capability while reducing the cumulative output loading that would result from multiple simultaneous drivers.
3Device complexity
If a single driver is used to output multiple data signals, then device complexity is reduced, but signal selection control becomes more complex
Solution Approach 1:
The patent introduces transfer gates as intermediary components between the multiple data signals and the single driver. These transfer gates act as mediators that simplify the control logic by providing clear, binary selection mechanisms (gate open/closed states) that determine which data signal reaches the driver, thereby managing the complexity of signal selection in a systematic way.
Data Source
AI summary
A multiplexer includes a first inverter for receiving and inverting first data, a second inverter for receiving and inverting second data, and a first driver connected to an output of the first inverter and to an output of the second inverter. The first driver is configured to output the first data or the second data as output data.