Shared ECC Decoder Architecture for Multi-Channel Flash Memory
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Solution Overview
Problem
Flash memory systems face increased complexity and cost due to the need for more ECC modules as they incorporate more memory devices and multi-level cell NAND memory, which enlarges the integrated circuit and increases ECC IP core gates, necessitating a more efficient use of area and circuitry for error detection and correction.
Innovation Solution
A memory system with a memory controller featuring multiple communication channels, error detectors, and a shared error correction mechanism that allows for parallel data encoding and decoding across channels, utilizing a multiplexer to share resources and operate in a pipelined mode with buffer memories for efficient error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more ECC modules are added to support more memory devices and MLC NAND memory, then error detection and correction capability is improved, but integrated circuit size and ECC IP core gates increase
Solution Approach 1:
The patent merges multiple ECC modules into a single shared ECC module that sequentially serves multiple memory devices. The controller includes one ECC module that can be dynamically allocated to different memory devices through channel switching, eliminating the need for separate ECC modules for each memory device while maintaining comprehensive error correction capability across all channels.
Solution Approach 2:
The single ECC module is designed to perform multiple functions by serving different memory devices and channels sequentially. The controller implements a universal ECC architecture that can handle encoding and decoding operations for any of the N memory devices through time-multiplexed resource allocation, making the ECC module adaptable to various memory channels.
2Reliability
If more ECC modules are added to support more memory devices and MLC NAND memory, then error detection and correction capability is improved, but ECC IP core gates increase
Solution Approach 1:
The patent combines the functionality of multiple ECC IP cores into a single shared ECC module. Instead of implementing separate ECC IP cores for each memory device, the system uses one ECC module that is time-multiplexed across multiple channels, significantly reducing the total number of gates required while maintaining equivalent error correction coverage.
Solution Approach 2:
The ECC module operates dynamically by switching between different memory devices and channels based on current operation requirements. The controller implements dynamic resource allocation where the single ECC module is assigned to different channels sequentially, allowing the system to adapt to varying memory access patterns without requiring static dedicated ECC resources for each device.
3Reliability
If separate ECC modules are used for each communication channel, then error correction reliability is improved, but area utilization efficiency deteriorates
Solution Approach 1:
The patent merges the error correction functionality across all communication channels into a single shared ECC module. This consolidation maintains full error correction capability for each channel while eliminating redundant ECC circuitry, thereby improving area utilization efficiency without sacrificing reliability.
Solution Approach 2:
The shared ECC module operates continuously by sequentially processing error correction tasks from different channels. While one channel undergoes error correction, the module can prepare for or process operations from other channels in a pipelined manner, ensuring continuous useful action and maintaining reliable error correction across all channels without idle time.
Data Source
AI summary
A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.