Shared-Electrode Capacitor Stack for Higher Capacitance Density
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Solution Overview
Problem
The challenge in scaling down semiconductor devices is to improve quality, yield, performance, and reliability while reducing complexity, particularly in achieving increased capacitance density.
Innovation Solution
A semiconductor device design featuring stacked and electrically parallel coupled capacitor units, with a bottom conductive structure, shared conductive layer, and top conductive layer separated by insulating layers, and connected via a conductive structure, enhancing capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor structures are used in scaled-down semiconductor devices, then device complexity is reduced, but capacitance density decreases
Solution Approach 1:
The patent implements nested capacitor structures where a first capacitor is formed within a trench and a second capacitor is formed above it, sharing common conductive layers. This nesting approach increases capacitance density by vertically stacking capacitive elements in the same footprint area, effectively placing one capacitor inside another spatial configuration.
Solution Approach 2:
The patent transitions from planar capacitor layouts to three-dimensional stacked structures by forming capacitors in vertical layers. The first capacitor resides in a trench while the second capacitor is positioned above it, utilizing the vertical dimension to increase capacitance density without expanding the lateral footprint.
2Quantity of substance
If multiple separate capacitor structures are formed, then capacitance density increases, but manufacturing complexity increases
Solution Approach 1:
The patent merges the manufacturing processes for multiple capacitors by forming both the first and second capacitors through integrated deposition and etching sequences. Common conductive layers are deposited once and then selectively patterned to serve multiple capacitor structures, reducing the total number of separate manufacturing steps.
Solution Approach 2:
The shared conductive layers serve multiple functions simultaneously - acting as the top electrode for the first capacitor and the bottom electrode for the second capacitor. This multi-functionality reduces the total number of conductive layers needed and simplifies the overall manufacturing process.
3Productivity
If capacitor size is reduced for scaling, then device integration increases, but capacitance value decreases
Solution Approach 1:
The patent compensates for reduced individual capacitor size by stacking capacitors vertically in multiple layers. The first capacitor is formed in a trench while the second capacitor is positioned above it, utilizing the vertical dimension to maintain total capacitance value while reducing the lateral footprint for higher device integration.
Solution Approach 2:
The nested configuration allows multiple capacitive elements to occupy the same lateral footprint area by positioning them at different vertical levels. This nesting approach maintains high capacitance values while enabling greater device integration density.
Data Source
AI summary
The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.