Shared Error-Check Circuit for Two-Cycle Data Integrity
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Solution Overview
Problem
The duplication of error-check signal generating circuitry for each set of payload flip-flops in conventional error check circuitry leads to significant silicon area, timing, and power overhead, especially in large circuits like processors.
Innovation Solution
A circuit design that captures the payload signal twice and uses the same logic for both generating and checking parity or ECC information, eliminating the need for duplicate error-check signal generating circuitry by reusing the same circuitry on different clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duplicate error-check signal generating circuitry is used at both input and output of payload flip-flops, then error detection reliability is improved, but silicon area consumption increases significantly
Solution Approach 1:
The patent merges the input and output error-check signal generating circuitry into a single shared circuit. The same error-check circuit generates parity bits for incoming data and verifies outgoing data, eliminating the need for duplicate circuitry while maintaining error detection capability across both data entry and exit points
Solution Approach 2:
The error-check signal generating circuit is designed to perform multiple functions: it generates error-check bits for input data, stores them in flip-flops, and subsequently verifies output data. This multi-functional approach allows a single circuit to replace what would traditionally require separate dedicated circuits for each function
2Reliability
If duplicate error-check signal generating circuitry is implemented, then error detection coverage is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple error-check operations into a single shared circuit that serves both input and output data paths. By consolidating the error-check signal generating circuitry, the total power consumption is reduced compared to having separate dedicated circuits for each operation
3Reliability
If duplicate error-check signal generating circuitry is used, then error checking capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error-check circuitry into a unified structure that handles both input and output verification. This consolidation reduces the number of separate components and interconnections required, thereby simplifying the overall device architecture while preserving comprehensive error checking capability
Solution Approach 2:
The shared error-check circuit is designed to perform multiple functions within a single unified structure, reducing device complexity by eliminating redundant components. The circuit adapts its operation based on whether it is generating error-check bits for input data or verifying error-check bits for output data
Data Source
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AI summary
A set of payload flip-flops receives an input instance of a payload, and outputs an output instance from which a first instance of an error check signal is generated. One or more error check flip-flops receive the first instance and output a second instance. The input payload instance is clocked into the payload flip-flops if a payload enable signal is asserted, and the first error-check signal instance is clocked into the error check flip-flops if an error check enable signal is asserted. The input payload instance is input to the set of payload flip-flops over two clock cycles, and the payload enable signal is asserted for the two clock cycles. The error check enable signal is asserted on the second cycle. The first instance of the error check signal is compared with the second instance and an error signal is asserted if they do not match.