Shared Fail Address Registers for Memory Decoder Area Reduction
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Solution Overview
Problem
As memory devices increase in capacity, the size of the memory cell array and the area required for registers storing fail addresses also increase, leading to inefficiencies in driving selection lines and potentially worsening the driving ability of column and row decoders.
Innovation Solution
The implementation of a memory device with dual decoders (column and row) that operate in opposite directions, sharing registers and write circuits to store fail addresses, allowing for reduced area usage and improved driving efficiency by merging the locations of these registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If registers storing fail addresses are disposed in all the circuits to repair fail memory cells, then the reliability of the memory device is improved, but the area of the memory device increases
Solution Approach 1:
The patent merges the locations of registers storing fail addresses by implementing a shared fail address register structure across multiple column decoders. Instead of providing separate registers in each decoder circuit, the invention uses a common register location that is shared by all column decoders, thereby reducing the total area while maintaining the ability to repair fail memory cells in any bank.
Solution Approach 2:
The shared fail address register structure serves multiple functions simultaneously - it stores fail addresses for multiple banks and serves multiple column decoders. This universal register structure eliminates the need for redundant register instances in each decoder, achieving area reduction while preserving repair functionality across the entire memory device.
2Quantity of substance
If the capacity of the memory device increases, then the storage capability is improved, but the area required for registers and circuits increases
Solution Approach 1:
The invention merges the fail address register functionality across multiple decoder circuits into a shared register structure. This allows the memory device to scale in capacity without proportionally increasing the area dedicated to register storage, as the shared register structure serves the entire expanded memory array efficiently.
3Quantity of substance
If the size of the memory cell array increases, then the storage capacity is improved, but the driving ability of column and row decoders deteriorates
Solution Approach 1:
The patent divides the large memory cell array into multiple banks, each with its own column decoder. By segmenting the array and using shared fail address registers across these segmented decoders, the invention maintains effective driving capability for each decoder while supporting a large overall array capacity. The segmentation prevents any single decoder from being overloaded.
Data Source
AI summary
A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.