Shared GPU Cache Isolation for Side-Channel Resistance

The cache is segmented into multiple isolated cache partitions, each dedicated to a specific tenant or compute context. This segmentation prevents side-channel attacks by ensuring that cache accesses from one tenant cannot be observed or exploited by other tenants, while still allowing each partition to be fully utilized for its designated workload.

A cache management intermediary layer is introduced between the compute contexts and the physical cache. This intermediary handles address translation, cache allocation, and access control, mediating all cache operations to ensure security policies are enforced while maintaining efficient cache utilization for multi-tenancy.

An address translation intermediary (such as a translation lookaside buffer or address translation unit) is positioned between the physical address generator and the cache array. This intermediary translates physical addresses into cache indices while enforcing access permissions, allowing fast physical addressing without exposing the raw physical address to the cache structure where it could be exploited for unauthorized access.

Different security properties are applied to different parts of the addressing mechanism. The physical address translation and permission checking are performed in a secure intermediary layer, while the actual cache access uses simplified indexing. This local differentiation of security requirements allows high-speed access where security is less critical while maintaining strong security where address translation occurs.