Shared I/Q Phase Interpolator for Low-Jitter Clock Recovery
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Solution Overview
Problem
Conventional phase interpolators in serial-link transceivers suffer from significant nonlinearity issues, leading to increased clock jitter and potential failure in clock and data recovery functionality, due to the use of non-ideal clock phases and the need for additional digital-to-analog converters (DACs) that increase parasitic capacitance and power consumption.
Innovation Solution
A phase interpolator design that incorporates a shared I/Q phase technique using configurable digital-to-analog converters (DACs), where some DACs can function as either I-DACs or Q-DACs, reducing the overall number of DACs required and minimizing parasitic capacitance, while maintaining low amplitude variation and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional phase interpolator uses a fixed number of I and Q components with reduced DACs, then hardware cost is reduced, but the output exhibits large nonlinearity and increased clock jitter
Solution Approach 1:
The patent implements dynamic reconfiguration of DAC functionality between I and Q modes based on control signals. The third plurality of DACs can be dynamically assigned to either I or Q components depending on the desired output phase, allowing the system to adapt its configuration rather than being fixed. This dynamic approach enables maintaining constant total components while achieving better linearity across different phase outputs.
Solution Approach 2:
The patent changes the operational parameters of DACs by switching their function between I-mode and Q-mode. By controlling which phase signal (I or Q) each DAC processes, the system can optimize the distribution of components to reduce nonlinearity. The control circuit adjusts the operational state of each DAC based on the required output phase, thereby improving phase linearity without increasing hardware count.
2Manufacturing precision
If additional DACs are added to improve phase accuracy, then phase accuracy is improved, but parasitic capacitance and power consumption increase
Solution Approach 1:
The patent makes DACs multi-functional by enabling them to operate in either I-mode or Q-mode based on control signals. The third plurality of DACs serves dual purposes: they can be assigned to process I components or Q components depending on the required output phase. This universality eliminates the need for dedicated separate DACs for each function, reducing total DAC count while maintaining phase accuracy.
Solution Approach 2:
The patent merges the functionality of I-DACs and Q-DACs into a shared pool of configurable DACs. Instead of having separate fixed assignments, the system combines the third plurality of DACs with both I and Q input signals, allowing them to be dynamically allocated. This merging reduces the total number of DACs required while achieving the same or better phase accuracy through optimized resource utilization.
3Device complexity
If the sum of I and Q components is kept constant, then hardware cost is reduced, but amplitude variation increases
Solution Approach 1:
The patent dynamically adjusts the allocation of configurable DACs between I and Q components based on the desired output phase. Rather than maintaining a fixed sum, the control circuit optimizes the distribution in real-time to compensate for amplitude variations. This dynamic reconfiguration allows the system to maintain constant total components while actively managing amplitude consistency across different phase outputs.
Data Source
AI summary
A phase interpolator is described. The phase interpolator may comprise a first plurality of digital-to-analog converters coupled to receive a first phase of a clock signal; a second plurality of digital-to-analog converters coupled to receive a second phase of the clock signal; and a third plurality of digital-to-analog converters coupled to both the first phase of the clock signal and the second phase of the clock; wherein each digital-to-analog converter is configurable to receive either the first phase of the clock signal or the second phase of the clock signal. A method of implementing a phase interpolator is also described.