Shared Loop Cache Instances for Multithreaded Processor Power Savings

Solution Overview

Problem

Conventional processor devices inefficiently utilize loop cache instances in multithread processing, leading to unrealized power savings due to the need for multiple loop cache instances for each thread executing a loop, resulting in inefficient operation.

Innovation Solution

A loop cache controller circuit shares loop cache instances among multiple threads by using use bit registers to track thread associations with loop cache instances, allowing retrieval of loop instructions from shared cache instances instead of the instruction cache.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple loop cache instances are provided for each thread executing a loop, then loop handling capability is improved, but device complexity and power consumption increase

Engineering Contradiction:

Improveloop handling capabilityVSAvoidnumber of loop cache instances

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges loop cache instances across multiple threads by implementing a shared loop cache structure. Instead of providing separate loop cache instances for each thread, the system allows multiple threads to share common loop cache instances, reducing the total number of cache instances required while maintaining loop handling capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent makes loop cache instances universal by enabling them to serve multiple threads simultaneously. The loop cache controller is designed to detect loops in different threads and direct them to appropriate shared cache instances, allowing each cache instance to perform the same function for multiple threads rather than having dedicated instances.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If multiple loop cache instances are provided for each thread executing a loop, then loop handling capability is improved, but power consumption increases

Engineering Contradiction:

Improveloop handling capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges loop cache instances across multiple threads by implementing a shared loop cache structure. Instead of providing separate loop cache instances for each thread, the system allows multiple threads to share common loop cache instances, reducing the total number of cache instances required while maintaining loop handling capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent makes loop cache instances universal by enabling them to serve multiple threads simultaneously. The loop cache controller is designed to detect loops in different threads and direct them to appropriate shared cache instances, allowing each cache instance to perform the same function for multiple threads rather than having dedicated instances.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If separate loop cache instances are allocated to each thread, then thread-specific loop caching is improved, but resource utilization efficiency deteriorates

Engineering Contradiction:

Improvethread-specific loop cachingVSAvoidresource utilization efficiency

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent makes loop cache instances universal by enabling them to serve multiple threads simultaneously. The loop cache controller is designed to detect loops in different threads and direct them to appropriate shared cache instances, allowing each cache instance to perform the same function for multiple threads rather than having dedicated instances.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements dynamic thread-to-cache instance mapping where the association between threads and loop cache instances is not fixed but can change based on runtime conditions. The loop cache controller dynamically detects which thread is executing which loop and directs them to appropriate cache instances, allowing flexible resource allocation that adapts to changing execution patterns.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12450060B1Sharing loop cache instances among multiple threads in processor devices

Publication Date: 2025.10.21 QUALCOMM INC

AI summary

Sharing loop cache instances among multiple threads in processor devices is disclosed herein. In some aspects, a processor device provides a loop cache controller circuit that is configured to detect a first iteration of a loop body, comprising a plurality of loop instructions, in an instruction stream executed by a first thread. The loop cache controller circuit determines that the loop instructions were previously stored in a loop cache instance associated with a second thread, and, in response, sets a use bit corresponding to the first thread of a use bit register corresponding to the loop cache instance. Upon detecting a subsequent iteration of the loop body by the first thread, the loop cache controller circuit retrieves the plurality of loop instructions from the loop cache instance instead of an instruction cache, based on the use bit corresponding to the first thread.