Shared Mantissa Adder for Fixed- and Floating-Point Processing

The patent implements a unified adder structure that can process both fixed-point and floating-point data types through a single circuit. The adder uses a shared mantissa addition unit that handles both data types by interpreting inputs differently: for floating-point operations, it adds mantissas after exponent alignment; for fixed-point operations, it directly adds numerical bits. This multi-functional design eliminates the need for separate adder circuits while maintaining processing accuracy for both data types.

The adder incorporates dynamic control mechanisms that adapt its operation based on the input data type. Control logic dynamically selects between floating-point processing mode (with exponent matching and mantissa addition) and fixed-point processing mode (with direct numerical bit addition). This dynamic behavior allows the same hardware structure to efficiently handle different data types without requiring static separate circuits for each type.

The patent changes the operational parameters of the adder based on data type requirements. For fixed-point data, the adder operates in a simplified mode that skips exponent matching and directly performs numerical bit addition, reducing power consumption. For floating-point data, the adder activates the full floating-point processing sequence including exponent comparison, mantissa alignment, and normalization. This parameter adaptation allows the system to consume only the necessary power for the required accuracy level.

The adder dynamically adjusts its operational complexity based on the input data type. When processing fixed-point data, the circuit disables the floating-point specific modules (exponent matching unit, normalization unit) and activates only the essential addition logic, thereby reducing power consumption. When floating-point data is detected, the full processing chain is activated to ensure accuracy. This dynamic configuration optimizes the power-accuracy tradeoff.

The adder performs preliminary classification of input data types at the beginning of the processing pipeline. Control logic immediately identifies whether inputs are fixed-point or floating-point and pre-configures the processing path accordingly. For floating-point inputs, exponent matching begins immediately in parallel with mantissa preparation. This preliminary action eliminates the need for sequential format conversion steps, reducing overall processing delay while maintaining compatibility with both data types.

The adder structure is segmented into independent processing paths: a floating-point path with exponent matching and mantissa addition, and a fixed-point path with direct numerical bit addition. Control logic segments the data flow into the appropriate path based on input type detection. This segmentation allows each path to be optimized independently and eliminates the need for format conversion between data types, as each path natively handles its designated data type without requiring transformation.

The carry look-ahead mechanism is dynamically activated only when processing floating-point data that requires mantissa addition. For fixed-point data processing, the adder uses a simpler carry propagation scheme that consumes less power. The control logic detects the data type and enables the power-intensive carry look-ahead circuits only when their speed benefits are necessary for floating-point mantissa operations, thereby optimizing the speed-power tradeoff.

The adder changes its carry propagation parameter based on the operation type. For floating-point mantissa addition, it uses carry look-ahead logic with generate and propagate signals to achieve fast parallel computation. For fixed-point addition, it switches to a lower-power carry propagation mode. This parameter change allows the system to achieve high-speed calculation when needed while reducing power consumption during operations that don't require the full carry look-ahead capability.