Shared Memory Repair Circuit for Lower Chip Area

Solution Overview

Problem

As memory capacity increases in memory devices, the size of memory cell arrays and the area required for repair circuits to address fail memory cells also grows, leading to increased chip size and power consumption.

Innovation Solution

A repair circuit is implemented by merging row repair circuits for every two memory banks, incorporating fail address latches, multiplexers, comparison circuits, logic operators, and valid hit latches to efficiently manage fail addresses and reduce chip size and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate repair circuits are provided for each memory bank, then repair reliability is improved, but chip area and power consumption increase

Engineering Contradiction:

Improverepair reliabilityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges repair circuits for multiple memory banks into a shared configuration. Specifically, a single repair circuit is designed to serve multiple banks by selectively receiving and processing fail addresses from different banks through multiplexers, thereby reducing the total number of repair circuits needed while maintaining repair capability across all banks.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared repair circuit is designed with universal functionality to handle repair operations for multiple memory banks. The circuit can selectively process fail addresses from any of the multiple banks through bank select signals and multiplexers, making a single circuit perform the repair function that would otherwise require multiple separate circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If separate repair circuits are provided for each memory bank, then repair functionality is improved, but power consumption increases

Engineering Contradiction:

Improverepair functionalityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges repair circuits for multiple memory banks into a shared configuration. Specifically, a single repair circuit is designed to serve multiple banks by selectively receiving and processing fail addresses from different banks through multiplexers, thereby reducing the total number of repair circuits needed while maintaining repair capability across all banks.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared repair circuit is designed with universal functionality to handle repair operations for multiple memory banks. The circuit can selectively process fail addresses from any of the multiple banks through bank select signals and multiplexers, making a single circuit perform the repair function that would otherwise require multiple separate circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Quantity of substance

If memory capacity is increased, then storage capability is improved, but chip area increases

Engineering Contradiction:

Improvememory capacityVSAvoidchip area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent merges repair circuits for multiple memory banks into a shared configuration. Specifically, a single repair circuit is designed to serve multiple banks by selectively receiving and processing fail addresses from different banks through multiplexers, thereby reducing the total number of repair circuits needed while maintaining repair capability across all banks.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12518848B2Memory device including repair circuit and operating method thereof

Publication Date: 2026.01.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A repair circuit, including a first fail address latch configured to latch a first fail address and a second fail address corresponding to a first bank; a second fail address latch configured to latch a third fail address and a fourth fail address corresponding to a second bank different from the first bank; a fail address multiplexer configured merge the first fail address and the third fail address into a first merge address, and to merge the second fail address and the fourth fail address into a second merge address; a comparison circuit configured to compare the first and second merge addresses with merged decoded row addresses to generate first and second hit signals; a logic operator configured to output a valid hit pre-signal based on the first and second hit signals; and a valid hit latch configured output a valid hit signal based on the valid hit pre-signal.