Shared Multiplier Circuit for Integer, Floating Point, and Vector Operations
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Solution Overview
Problem
Modern processors face challenges in efficiently performing various types of multiplication operations due to the large resource-intensive nature of separate multipliers, which occupy significant die space, limiting the availability of space for other circuits.
Innovation Solution
A shared multiplier circuit is designed to perform integer, floating point, polynomial, scalar, and vector multiply operations, utilizing encoders and multiplexers to select and combine partial products through a carry save adder tree, allowing for efficient operation on different operand bit-lengths and modes within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate multipliers are implemented for each multiplication type (integer, floating point, polynomial, vector), then each multiplication operation can be performed with dedicated circuitry, but the die space consumed by multiplier circuits increases significantly
Solution Approach 1:
The patent implements a universal multiplier circuit that can perform multiple types of multiplication operations (integer, floating point, polynomial, vector) using the same hardware resources. The multiplier includes control logic that configures the circuitry differently based on the operation type, allowing one multiplier to replace what would traditionally require multiple separate multipliers, thereby reducing die space while maintaining support for all multiplication types
Solution Approach 2:
The multiplier circuit employs dynamic configuration through control signals that reconfigure the circuitry based on the type of multiplication operation required. The same physical circuit can be dynamically adapted to perform different multiplication types by changing its operational mode, enabling flexible resource utilization without requiring dedicated static circuitry for each operation type
2Adaptability or versatility
If multiple separate multipliers are implemented to handle different operation types, then operational flexibility is maintained, but the number of multiplier circuits increases reducing space for other circuits
Solution Approach 1:
The patent creates a single multiplier circuit capable of performing multiple operation types (scalar, vector, polynomial, integer, floating point multiplication) through dynamic configuration. This universal approach maintains operational flexibility while reducing the total number of multiplier circuits from multiple separate multipliers to one shared resource, thereby reducing device complexity
3Area of stationary object
If a shared multiplier is implemented to reduce die space, then the number of multiplier circuits is reduced, but the complexity of controlling the shared resource increases
Solution Approach 1:
The patent introduces control logic as an intermediary layer that manages the shared multiplier resource. This control logic receives operation type information, configures the multiplier appropriately, and coordinates the execution of different multiplication operations. By placing this intermediary control layer, the complexity is centralized and managed systematically rather than distributed across multiple independent multipliers, making the system more efficient overall
Data Source
AI summary
A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.