Shared-Node Clock Gating to Minimize Setup Time Skew
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Solution Overview
Problem
Clock gaters in integrated circuits face a setup time issue due to race conditions between clock signals and latch outputs, leading to potential clock skew problems, which can be exacerbated by the need to delay clock signals through additional setup operations.
Innovation Solution
A clock gater design that includes a dynamic logic gate and a latch sharing nodes, with a keeper and feedback subcircuit, allowing for simultaneous reception of clock and enable signals, thereby minimizing setup time and surface area while preventing clock skew by controlling node voltages based on clock states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional setup operations are added to delay clock signals, then clock skew problems are prevented, but setup time increases and device complexity increases
Solution Approach 1:
The patent combines the latch output and clock signal paths to share common nodes (nodes A and B), eliminating the need for separate delay circuits. The latch and clock gater logic are merged into a single integrated structure, allowing simultaneous signal reception without additional setup time while maintaining clock skew prevention through shared node voltage control.
Solution Approach 2:
The patent employs feedback mechanisms where the latch output feeds back to control the clock gater logic through shared nodes. The voltage states at nodes A and B are dynamically controlled based on feedback from both the latch output and clock signal, enabling automatic synchronization without external delay operations.
2Reliability
If additional setup operations are added to delay clock signals, then clock skew problems are prevented, but device complexity increases
Solution Approach 1:
The patent merges the clock gater logic and latch into a single integrated circuit structure that shares common nodes A and B. This consolidation reduces the number of separate components and interconnections, simplifying the overall device structure while maintaining the functionality of both the latch and clock gating operations.
Solution Approach 2:
The shared nodes A and B serve multiple functions: they act as output nodes for the latch, input nodes for the clock gater logic, and control points for preventing clock skew. This multi-functionality reduces the need for dedicated components for each function, thereby reducing overall device complexity.
3Reliability
If clock signals are delayed through additional setup operations, then clock skew is prevented, but surface area increases
Solution Approach 1:
By merging the latch and clock gater into a single structure that shares nodes A and B, the patent reduces the total surface area required. The shared nodes eliminate the need for separate delay circuitry and reduce the number of interconnections, thereby minimizing the overall layout area of the clock gater circuit.
4Loss of energy
If clock gaters are used to inhibit clock signals, then power consumption is reduced, but setup time issues arise due to race conditions
Solution Approach 1:
The patent combines the power management functionality of the clock gater with the latch circuit, allowing the same shared nodes to control both power gating and signal latching. This integration ensures that the enable signal is properly synchronized with the clock signal without requiring additional setup time, while still achieving power savings by gating the clock to power-consuming circuits.
Data Source
AI summary
A clock gater includes a first logic circuit that receives an enable signal and that includes first and second subcircuits. The clock gater also includes a latch that shares first and second nodes with the first logic circuit and that includes third and fourth subcircuits. The first logic circuit and the latch receive a clock signal that varies between first and second clock states. The first and third subcircuits pull the first and second nodes, respectively, to a common precharge voltage based on the first clock state in order to pass the clock signal. The second and fourth subcircuits pull the first and second nodes, respectively, to complementary voltages based on the second clock state to pass the clock signal. The first node passes the clock signal or gates the clock signal based on the enable signal.