Shared Floating-Diffusion Pixel Array for CMOS Noise Reduction

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Solution Overview

Problem

Existing CMOS image sensors face challenges in reducing noise due to the inability to use drive transistors and select transistors of neighboring pixels sharing a floating diffusion region when connected to different output lines.

Innovation Solution

A pixel array structure is introduced where two unit pixel groups share a floating diffusion region and are connected to one column line, with signal lines configured to transfer pixel signals through shared floating diffusion regions, incorporating a reset transistor and a dual conversion transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If pixels sharing a floating diffusion region are connected to different output lines, then device complexity is reduced, but noise reduction capability is lost

Engineering Contradiction:
Improveoutput line configurationVSAvoidnoise
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent merges the readout paths of adjacent pixel groups by connecting them to a shared column line. Two pixel groups that share a floating diffusion region are configured to output their signals through the same column line, allowing the drive transistors and select transistors of neighboring pixels to be utilized for noise reduction while maintaining connection to a single output line.

Inventive Principle:
Principle #5Merging (Combining)

2Object-generated harmful factors

If drive transistors and select transistors of neighboring pixels are used for noise reduction, then noise is reduced, but this requires pixels to be connected to the same output line

Engineering Contradiction:
ImprovenoiseVSAvoidoutput line configuration
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent combines multiple pixel groups into a shared readout path. Specifically, first and second pixel groups that share a floating diffusion region are both connected to the same column line, enabling the utilization of drive transistors and select transistors for correlated noise reduction while maintaining a simplified output structure.

Inventive Principle:
Principle #5Merging (Combining)

3Object-generated harmful factors

If two unit pixel groups share a floating diffusion region and connect to one column line, then noise reduction and transconductance increase are achieved, but photo response non-uniformity must be minimized

Engineering Contradiction:
ImprovenoiseVSAvoidphoto response uniformity
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent implements local quality control by providing independent reset transistors and dual conversion transistors to each pixel group within the shared floating diffusion region. This allows for localized adjustment and compensation of photo response characteristics, minimizing non-uniformity while maintaining the noise reduction benefits of shared readout paths.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration minimizes photo response non-uniformity and reduces noise such as random telegraph signals and random noise, while increasing transconductance and enabling efficient readout operations.

Implementation Method 1

convert light energy into an electrical signal using a photoelectric conversion element included in each pixel

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS12549871B2Pixel array with structure for noise reduction and image sensor including the same
Publication Date: 2026.02.10 SAMSUNG ELECTRONICS CO LTD
  • US12549871B2 patent drawing
  • US12549871B2 patent drawing
  • US12549871B2 patent drawing

AI summary

A pixel array includes: a plurality of unit pixel groups; and one or more columns including four column lines, wherein each unit pixel group of the plurality of unit pixel groups includes a first pixel group and a second pixel group, wherein the each unit pixel group includes a signal line including a drive transistor and a select transistor, wherein two unit pixel groups share a floating diffusion region, and wherein signal lines of the two unit pixel groups are connected to one column line, wherein each of the two unit pixel groups is configured to transfer a pixel signal to the one column line through the signal lines, wherein the floating diffusion region is located between a reset transistor and a dual conversion transistor, and wherein the dual conversion transistor is connected to the reset transistor and the drive transistor.